Re: [PATCH resend v8 0/5] phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support

On Wed, 2022-04-20 at 13:00 +0530, Vinod Koul wrote:

On 19-04-22, 09:08, Liu Ying wrote:

quoted

Hi,

This is the v8 series to add i.MX8qxp LVDS PHY mode support for the
Mixel
PHY in the Freescale i.MX8qxp SoC.

The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in
either
MIPI DPHY mode or LVDS PHY mode.  The PHY mode is controlled by
i.MX8qxp
SCU firmware.  The PHY driver would call a SCU function to
configure the
mode.

The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq
SoC,
where it appears to be a single MIPI DPHY.


Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host
controller
bridge driver, since i.MX8qxp SoC embeds this controller IP to
support
MIPI DSI displays together with the Mixel PHY.

Patch 2/5 allows LVDS PHYs to be configured through the generic PHY
functions
and through a custom structure added to the generic PHY
configuration union.

Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to
json-schema.

Patch 4/5 adds dt binding support for the Mixel combo PHY in
i.MX8qxp SoC.

Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY
driver.

Applied patch 2-5 to phy-next, thanks

Now that patch 2-5 landed in phy-next, patch 1 is needed to explicitly
set MIPI DPHY mode in the nwl-dsi drm bridge driver, otherwise, i.MX8mq
MIPI DSI display feature will be broken due to the phy mode check added
in patch 5.

I'm assuming patch 1 should go through drm-misc. Robert/drm folks, can
you please pick it up?

Thanks,
Liu Ying


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