[PATCH 2/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
From: Jianjun Wang <hidden>
Date: 2022-03-11 13:35:54
Also in:
linux-devicetree, linux-mediatek, linux-phy, lkml
Subsystem:
arm/mediatek usb3 phy driver, generic phy framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Chunfeng Yun, Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by: Jianjun Wang <redacted> --- .../bindings/phy/mediatek,pcie-phy.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
new file mode 100644
index 000000000000..da15b4bf3117
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml@@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIe PHY Device Tree Binding + +maintainers: + - Jianjun Wang <jianjun.wang@mediatek.com> + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. + +properties: + compatible: + const: mediatek,pcie-phy + + reg: + maxItems: 1 + + reg-names: + items: + - const: sif + + "#phy-cells": + const: 0 + + nvmem-cells: + maxItems: 7 + description: + Phandles to nvmem cell that contains the efuse data, if unspecified, + default value is used. + + nvmem-cell-names: + items: + - const: glb_intr + - const: tx_ln0_pmos + - const: tx_ln0_nmos + - const: rx_ln0 + - const: tx_ln1_pmos + - const: tx_ln1_nmos + - const: rx_ln1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + pciephy: phy@11e80000 { + compatible = "mediatek,pcie-phy"; + #phy-cells = <0>; + reg = <0x11e80000 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, + <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, + <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, + <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + };
--
2.18.0
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