Re: [PATCH 2/6] spi: rockchip: Preset cs-high and clk polarity in setup progress

On Mon, Feb 14, 2022 at 04:40:19PM +0800, Jon Lin wrote:

在 2022/2/11 19:24, Mark Brown 写道:

quoted

quoted

+   cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
+   if (spi->mode & SPI_CS_HIGH)
+           cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;

quoted

What ensures that this read/modify/write doesn't race with a transfer
running on another client device in the case where the controller has
more than one device connected?  Similarly with the mode, though it's
not great to have devices with different modes connected to a single
controller.

I have no idea how to deal with the conflict configuration between
different cs, and also I find nothing strategy in others spi drivers.
As we all know, some configurations should be consistent for different
CS devices, such as SPI_CPOL, so I suggest the framework to make
corresponding early warning prompts.

As covered in the documentation setup() for one device may run while
another is active, therefore if multiple devices are configured in the
same register you should use a lock to ensure there can't be multiple
writes.  Note that the above appears to not just be setting the mode but
also the chip select so if you've got two SPI_CS_HIGH devices then
they'll both be going in and separately setting cr0.