@@ -165,6 +165,18 @@
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		BIT(17)
 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(BIT(17) | BIT(16))
 
+/* VPPSYS0 */
+#define VPPSYS0_HW_DCM_1ST_DIS0					0x050
+
+/* VPPSYS1 */
+#define VPPSYS1_HW_DCM_1ST_DIS0					0x150
+#define VPPSYS1_HW_DCM_1ST_DIS1					0x160
+#define VPPSYS1_HW_DCM_2ND_DIS0					0x1a0
+#define VPPSYS1_HW_DCM_2ND_DIS1					0x1b0
+#define VPP0_DL_IRELAY_WR					0x920
+#define SVPP2_BUF_BF_RSZ_SWITCH					0xf48
+#define SVPP3_BUF_BF_RSZ_SWITCH					0xf74
+
 static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 	{
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

@@ -217,4 +229,15 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 	}
 };
 
+static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = {
+	VPPSYS0_HW_DCM_1ST_DIS0,
+	VPP0_DL_IRELAY_WR,
+	VPPSYS1_HW_DCM_1ST_DIS0,
+	VPPSYS1_HW_DCM_1ST_DIS1,
+	VPPSYS1_HW_DCM_2ND_DIS0,
+	VPPSYS1_HW_DCM_2ND_DIS1,
+	SVPP2_BUF_BF_RSZ_SWITCH,
+	SVPP3_BUF_BF_RSZ_SWITCH,
+};
+
 #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */

@@ -79,10 +79,16 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 
 static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
 	.clk_driver = "clk-mt8195-vpp0",
+	.mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+	.mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+	.vppsys = true,
 };
 
 static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
 	.clk_driver = "clk-mt8195-vpp1",
+	.mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+	.mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+	.vppsys = true,
 };
 
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {

@@ -137,6 +143,18 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
 
+void mtk_mmsys_mdp_write_config(struct device *dev,
+				struct mmsys_cmdq_cmd *cmd,
+				u32 alias_id, u32 value, u32 mask)
+{
+	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+	const u32 *configs = mmsys->data->mdp_mmsys_configs;
+
+	cmdq_pkt_write_mask(cmd->pkt, mmsys->cmdq_base.subsys,
+			    mmsys->addr + configs[alias_id], value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_write_config);
+
 void mtk_mmsys_write_reg_by_cmdq(struct device *dev,
 				 struct mmsys_cmdq_cmd *cmd,
 				 u32 offset, u32 value, u32 mask)

@@ -367,6 +385,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	if (IS_ERR(clks))
 		return PTR_ERR(clks);
 
+	if (mmsys->data->vppsys)
+		goto EXIT;
+
 	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
 					    PLATFORM_DEVID_AUTO, NULL, 0);
 	if (IS_ERR(drm)) {

@@ -374,6 +395,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return PTR_ERR(drm);
 	}
 
+EXIT:
 	return 0;
 }
 

@@ -94,6 +94,9 @@ struct mtk_mmsys_driver_data {
 	const unsigned int num_routes;
 	bool has_gce_client_reg;
 	const unsigned int *mdp_isp_ctrl;
+	const u32 *mdp_mmsys_configs;
+	const unsigned int mdp_num_mmsys_configs;
+	bool vppsys;
 };
 
 /*

@@ -194,4 +194,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
 			      enum mtk_mdp_comp_id id,
 			      u32 camin_w, u32 camin_h);
 
+void mtk_mmsys_mdp_write_config(struct device *dev,
+				struct mmsys_cmdq_cmd *cmd,
+				u32 alias_id, u32 value, u32 mask);
+
 #endif /* __MTK_MMSYS_H */