This is the second round of the vop2 series. There are still some issues open,
but I thought it's about time to let people see and test it. I integrated the
review feedback I got from v1. Other changes include:
All framesync waiting is gone from the driver which makes it more straight
forward. To accomplish this the port_mux setup is now static in the driver.
This means each video port has a fixed maximum number of planes which is less
flexible but much easier to handle.
I also removed much of the register mapping and shadow register handling around
struct vop_reg. This basically resembles regmap and can eventually replaced by
regmap. Some places are still left in the driver, I plan to remove those in
later versions.
I think I have found the issue why only 1080p resolutions work, this seems to
be an issue in the way the clock tree is arranged. See the last patch in this
series which points to the problem, so far I don't have a good solution for it.
As usual, all comments and feedback welcome.
Sascha
Changes since v1:
- drop all unnecessary waiting for frames within atomic modeset and plane update
- Cluster subwin support removed
- gamma support removed
- unnecessary irq_lock removed
- interrupt handling simplified
- simplified zpos handling
- drop is_alpha_support(), use fb->format->has_alpha instead
- use devm_regulator_get() rather than devm_regulator_get_optional() for hdmi regulators
- Use fixed number of planes per video port
- Drop homegrown regmap code from vop2 driver (not complete yet)
- Add separate include file for vop2 driver to not pollute the vop include
Andy Yan (1):
drm: rockchip: Add VOP2 driver
Benjamin Gaignard (1):
dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568
HDMI
Michael Riesch (1):
arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a
Sascha Hauer (15):
drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
drm/rockchip: dw_hdmi: rename vpll clock to reference clock
drm/rockchip: dw_hdmi: add rk3568 support
drm/rockchip: dw_hdmi: add regulator support
dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional
dt-bindings: display: rockchip: dw-hdmi: Allow "ref" as clock name
dt-bindings: display: rockchip: dw-hdmi: Add regulator support
arm64: dts: rockchip: rk3399: reorder hmdi clocks
dt-bindings: display: rockchip: Add binding for VOP2
arm64: dts: rockchip: rk356x: Add VOP2 nodes
arm64: dts: rockchip: rk356x: Add HDMI nodes
arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
drm/encoder: Add of_graph port to struct drm_encoder
drm/rockchip: Make VOP driver optional
[HACK, RFC] clk: rk3568: do not divide dclk_vop0
.../display/rockchip/rockchip,dw-hdmi.yaml | 14 +-
.../display/rockchip/rockchip-vop2.yaml | 118 +
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +-
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 31 +
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 +
.../boot/dts/rockchip/rk3568-evb1-v10.dts | 31 +
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 75 +
drivers/clk/rockchip/clk-rk3568.c | 4 +-
drivers/gpu/drm/rockchip/Kconfig | 14 +
drivers/gpu/drm/rockchip/Makefile | 4 +-
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 107 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 3 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 7 +-
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 +
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 15 +
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2636 +++++++++++++++++
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 625 ++++
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 505 ++++
include/drm/drm_encoder.h | 2 +
include/dt-bindings/soc/rockchip,vop2.h | 14 +
21 files changed, 4193 insertions(+), 28 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
--
2.30.2
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Add a new dw_hdmi_plat_data struct and new compatible for rk3568.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 31 +++++++++++++++++++++
1 file changed, 31 insertions(+)
This enabled the VOP2 display controller along with hdmi and the
required port routes which is enough to get a picture out of the
hdmi port of the board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../boot/dts/rockchip/rk3568-evb1-v10.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock. The clock
name "vpll" is left for compatibility to old device trees.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++---------
1 file changed, 16 insertions(+), 13 deletions(-)
@@ -196,14 +196,17 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)returnPTR_ERR(hdmi->regmap);}-hdmi->vpll_clk=devm_clk_get(hdmi->dev,"vpll");-if(PTR_ERR(hdmi->vpll_clk)==-ENOENT){-hdmi->vpll_clk=NULL;-}elseif(PTR_ERR(hdmi->vpll_clk)==-EPROBE_DEFER){+hdmi->ref_clk=devm_clk_get(hdmi->dev,"ref");+if(PTR_ERR(hdmi->ref_clk)==-ENOENT)+hdmi->ref_clk=devm_clk_get(hdmi->dev,"vpll");++if(PTR_ERR(hdmi->ref_clk)==-ENOENT){+hdmi->ref_clk=NULL;+}elseif(PTR_ERR(hdmi->ref_clk)==-EPROBE_DEFER){return-EPROBE_DEFER;-}elseif(IS_ERR(hdmi->vpll_clk)){-DRM_DEV_ERROR(hdmi->dev,"failed to get vpll clock\n");-returnPTR_ERR(hdmi->vpll_clk);+}elseif(IS_ERR(hdmi->ref_clk)){+DRM_DEV_ERROR(hdmi->dev,"failed to get reference clock\n");+returnPTR_ERR(hdmi->ref_clk);}hdmi->grf_clk=devm_clk_get(hdmi->dev,"grf");
Add a device node to drm_encoder which corresponds with the port node
in the DT description of the encoder. This allows drivers to find the
of_graph link between a crtc and an encoder.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
include/drm/drm_encoder.h | 2 ++
1 file changed, 2 insertions(+)
From: Michael Riesch <redacted>
Enable the RK356x Video Output Processor (VOP) 2 on the Pine64
Quartz64 Model A.
Signed-off-by: Michael Riesch <redacted>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
The binding differs slightly from the existing VOP binding, so add a new
binding file for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../display/rockchip/rockchip-vop2.yaml | 118 ++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
@@ -0,0 +1,118 @@+# SPDX-License-Identifier: GPL-2.0+%YAML1.2+---+$id:http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Rockchip SoC display controller (VOP2)++description:+VOP2 (Video Output Processor v2) is the display controller for the Rockchip+series of SoCs which transfers the image data from a video memory+buffer to an external LCD interface.++maintainers:+-Sandy Huang <hjc@rock-chips.com>+-Heiko Stuebner <heiko@sntech.de>++properties:+compatible:+enum:+-rockchip,rk3566-vop+-rockchip,rk3568-vop++reg:+minItems:1+items:+-description:+Must contain one entry corresponding to the base address and length+of the register space.+-description:+Can optionally contain a second entry corresponding to+the CRTC gamma LUT address.++interrupts:+maxItems:1+description:+The VOP interrupt is shared by several interrupt sources, such as+frame start (VSYNC), line flag and other status interrupts.++clocks:+items:+-description:Clock for ddr buffer transfer.+-description:Clock for the ahb bus to R/W the phy regs.+-description:Pixel clock for video port 0.+-description:Pixel clock for video port 1.+-description:Pixel clock for video port 2.++clock-names:+items:+-const:aclk_vop+-const:hclk_vop+-const:dclk_vp0+-const:dclk_vp1+-const:dclk_vp2++port:+$ref:/schemas/graph.yaml#/properties/port++assigned-clocks:+maxItems:2++assigned-clock-rates:+maxItems:2++iommus:+maxItems:1++power-domains:+maxItems:1++required:+-compatible+-reg+-interrupts+-clocks+-clock-names+-port++additionalProperties:false++examples:+-|+#include <dt-bindings/clock/rk3568-cru.h>+#include <dt-bindings/interrupt-controller/arm-gic.h>+#include <dt-bindings/power/rk3568-power.h>+bus {+#address-cells = <2>;+#size-cells = <2>;+vop:vop@fe040000 {+compatible = "rockchip,rk3568-vop";+reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;+interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;+clocks = <&cru ACLK_VOP>,+<&cru HCLK_VOP>,+<&cru DCLK_VOP0>,+<&cru DCLK_VOP1>,+<&cru DCLK_VOP2>;+clock-names = "aclk_vop",+"hclk_vop",+"dclk_vp0",+"dclk_vp1",+"dclk_vp2";+power-domains = <&power RK3568_PD_VO>;+iommus = <&vop_mmu>;+vop_out:port {+#address-cells = <1>;+#size-cells = <0>;+vp0_out_dsi0:endpoint@0 {+reg = <0>;+remote-endpoint = <&dsi0_in_vp0>;+};+vp0_out_hdmi:endpoint@1 {+reg = <1>;+remote-endpoint = <&hdmi0_in_vp0>;+};+};+};+};
--
2.30.2
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@@ -28,6 +28,12 @@ properties:reg-io-width:const:4+avdd-0v9-supply:+description:A 0.9V supply that powers up the SoC internal circuitry.++avdd-1v8-supply:+description:A 1.8V supply that powers up the SoC internal circuitry.+clocks:minItems:2items:
--
2.30.2
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@@ -4,9 +4,10 @@# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.rockchipdrm-y:=rockchip_drm_drv.orockchip_drm_fb.o\-rockchip_drm_gem.orockchip_drm_vop.orockchip_vop_reg.o+rockchip_drm_gem.orockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION)+=rockchip_drm_fbdev.o+rockchipdrm-$(CONFIG_ROCKCHIP_VOP)+=rockchip_drm_vop.orockchip_vop_reg.orockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP)+=analogix_dp-rockchip.orockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP)+=cdn-dp-core.ocdn-dp-reg.orockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI)+=dw_hdmi-rockchip.o
The VOP2 is the display output controller on the RK3568. Add the node
for it to the dtsi file along with the required display-subsystem node
and the iommu node.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 51 ++++++++++++++++++++++++
include/dt-bindings/soc/rockchip,vop2.h | 14 +++++++
4 files changed, 73 insertions(+)
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
None of the upstream device tree files has a "unwedge" pinctrl
specified. Make it optional.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml | 1 +
1 file changed, 1 insertion(+)
@@ -73,6 +73,7 @@ properties:The unwedge pinctrl entry shall drive the DDC SDA line low. This isintended to work around a hardware errata that can cause the DDC I2Cbus to be wedged.+minItems:1items:-const:default-const:unwedge
--
2.30.2
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The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed
for the HDMI port. add support for these to the driver for boards which
have them supplied by switchable regulators.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++--
1 file changed, 38 insertions(+), 3 deletions(-)
Add support for the HDMI port found on RK3568.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 26 +++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
On the rk3568 we have this (simplified) situation:
.--------. .-----. .---------.
-| hpll |--.--| /n |----|dclk_vop0|-
`--------´ | `-----´ `---------´
| .-----. .---------.
`--| /m |----|dclk_vop1|-
| `-----´ `---------´
| .---------.
`-------------|hdmi_ref |-
`---------´
hpll is the PLL that drives the HDMI reference clock and the pixel
clocks for the different CRTCs (dclk_vop0/1). Between the pixel clocks
and the hpll there are programmable dividers whereas the HDMI reference
clock is directly connected to the hpll.
For the HDMI output to work the pixel clock must be the same as the HDMI
reference clock, hence the dividers must be programmed to 1. Normally a
rate change on dclk_vop0/1 propagates through to the hpll and the clock
framework picks a suitable combination of hpll and divider settings. by
accident it picks a divider setting of 1 for the standard 1080p case,
but other divider settings for most other resolutions leaving the HDMI
port non working.
This patch is not a solution, it merely puts the finger in the wound. We
leave out the divider for the composite clock for dclk_vop0 which then
leaves the divider at the bootloader default setting of 1. I assume
the divider is disturbing only for the HDMI case, but needed for other
outputs. Any thoughts how this can be handled?
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/rockchip/clk-rk3568.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock. The clock
name "vpll" is left for compatibility to old device trees.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../bindings/display/rockchip/rockchip,dw-hdmi.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Define a new compatible for rk3568 HDMI.
This version of HDMI hardware block needs two new clocks hclk_vio and hclk
to provide phy reference clocks.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210707120323.401785-2-benjamin.gaignard@collabora.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml | 1 +
1 file changed, 1 insertion(+)
@@ -28,6 +28,12 @@ properties:reg-io-width:const:4+avdd-0v9-supply:+description:A 0.9V supply that powers up the SoC internal circuitry.
Might be worth calling out the actual pin name so it's abundantly clear
for DT authors cross-referencing schematics. Annoyingly, some SoCs have
HDMI_AVDD_1V0 instead of HDMI_AVDD_0V9 - I'm not sure it's worth
splitting hairs that far in terms of the property name itself, but I'll
leave that for others to decide.
+ avdd-1v8-supply:
+ description: A 1.8V supply that powers up the SoC internal circuitry.
At least HDMI_AVDD_1V8 seems more consistent.
Thanks,
Robin.
Hi Sascha,
Am Mittwoch, 8. Dezember 2021, 16:12:30 CET schrieb Sascha Hauer:
On the rk3568 we have this (simplified) situation:
.--------. .-----. .---------.
-| hpll |--.--| /n |----|dclk_vop0|-
`--------´ | `-----´ `---------´
| .-----. .---------.
`--| /m |----|dclk_vop1|-
| `-----´ `---------´
| .---------.
`-------------|hdmi_ref |-
`---------´
hpll is the PLL that drives the HDMI reference clock and the pixel
clocks for the different CRTCs (dclk_vop0/1). Between the pixel clocks
and the hpll there are programmable dividers whereas the HDMI reference
clock is directly connected to the hpll.
For the HDMI output to work the pixel clock must be the same as the HDMI
reference clock, hence the dividers must be programmed to 1. Normally a
rate change on dclk_vop0/1 propagates through to the hpll and the clock
framework picks a suitable combination of hpll and divider settings. by
accident it picks a divider setting of 1 for the standard 1080p case,
but other divider settings for most other resolutions leaving the HDMI
port non working.
This patch is not a solution, it merely puts the finger in the wound. We
leave out the divider for the composite clock for dclk_vop0 which then
leaves the divider at the bootloader default setting of 1. I assume
the divider is disturbing only for the HDMI case, but needed for other
outputs. Any thoughts how this can be handled?
I'm not even sure if/how the common clock framework keeps track of
diverging wishes to parent-rates :-) .
But I do see two direct issues in the _existing_ code.
dclk_vop0/1 uses CLK_SET_RATE_PARENT so is allowed to change
the rates of its parent clock(s).
Its parent clocks are not only hpll but can also be vpll, gpll and cpll.
So this can cause even more mayhem, if the ccf for example decides
to select the gpll and then change its rate,which may result in a lot
of peripherals getting their rates changed under them ;-) .
On the other hand I see in the clock driver that hdmi-ref is not allowed
to change its parent rate, so can only select between hpll and hpll_ph0
(1/2 the rate?).
So I guess, one way could be:
- add CLK_SET_RATE_PARENT to the hdmi-ref clock
- drop CLK_SET_RATE_PARENT from the dclks
- make sure hdmi-clock is set before the dclk
Heiko
From: Johan Jonker <hidden> Date: 2021-12-08 17:30:28
Hi,
Could add a patch version to the subject?
On 12/8/21 4:12 PM, Sascha Hauer wrote:
quoted hunk
This enabled the VOP2 display controller along with hdmi and the
required port routes which is enough to get a picture out of the
hdmi port of the board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../boot/dts/rockchip/rk3568-evb1-v10.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
On Wed, Dec 08, 2021 at 05:51:43PM +0100, Heiko Stübner wrote:
Hi Sascha,
Am Mittwoch, 8. Dezember 2021, 16:12:30 CET schrieb Sascha Hauer:
quoted
On the rk3568 we have this (simplified) situation:
.--------. .-----. .---------.
-| hpll |--.--| /n |----|dclk_vop0|-
`--------´ | `-----´ `---------´
| .-----. .---------.
`--| /m |----|dclk_vop1|-
| `-----´ `---------´
| .---------.
`-------------|hdmi_ref |-
`---------´
hpll is the PLL that drives the HDMI reference clock and the pixel
clocks for the different CRTCs (dclk_vop0/1). Between the pixel clocks
and the hpll there are programmable dividers whereas the HDMI reference
clock is directly connected to the hpll.
For the HDMI output to work the pixel clock must be the same as the HDMI
reference clock, hence the dividers must be programmed to 1. Normally a
rate change on dclk_vop0/1 propagates through to the hpll and the clock
framework picks a suitable combination of hpll and divider settings. by
accident it picks a divider setting of 1 for the standard 1080p case,
but other divider settings for most other resolutions leaving the HDMI
port non working.
This patch is not a solution, it merely puts the finger in the wound. We
leave out the divider for the composite clock for dclk_vop0 which then
leaves the divider at the bootloader default setting of 1. I assume
the divider is disturbing only for the HDMI case, but needed for other
outputs. Any thoughts how this can be handled?
I'm not even sure if/how the common clock framework keeps track of
diverging wishes to parent-rates :-) .
I don't think the common clock framework tries to keep track of that.
But I do see two direct issues in the _existing_ code.
dclk_vop0/1 uses CLK_SET_RATE_PARENT so is allowed to change
the rates of its parent clock(s).
Its parent clocks are not only hpll but can also be vpll, gpll and cpll.
So this can cause even more mayhem, if the ccf for example decides
to select the gpll and then change its rate,which may result in a lot
of peripherals getting their rates changed under them ;-) .
Right, we can only allow the CLK_SET_RATE_PARENT parent flag on the dclk
clocks when the parent is HPLL. Since we can't be sure that HPLL is the
parent we have to remove the flag.
On the other hand I see in the clock driver that hdmi-ref is not allowed
to change its parent rate, so can only select between hpll and hpll_ph0
(1/2 the rate?).
So I guess, one way could be:
- add CLK_SET_RATE_PARENT to the hdmi-ref clock
- drop CLK_SET_RATE_PARENT from the dclks
- make sure hdmi-clock is set before the dclk
That solves it for the HDMI case. I can imagine that for a LVDS user the
CLK_SET_RATE_PARENT flag on the dclks is quite handy to get a PLL
frequency suitable for the display. Otherwise he would have to set a
suitable PLL frequency using assigned-clock-rates in the device tree.
That's still possible so this might be a good compromise.
Sascha
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Am Mittwoch, 8. Dezember 2021, 16:12:19 CET schrieb Sascha Hauer:
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock. The clock
name "vpll" is left for compatibility to old device trees.
Can't we just say that the binding only takes the "ref" name, but
the code still allows "vpll".
I think I remember Rob suggesting something similar in the past.
I don't think that we need to keep the binding(-validation)
compatible with old devicetrees, but the kernel itself should stay
compatible.
Heiko
On Sun, Dec 12, 2021 at 11:09:24PM +0100, Heiko Stuebner wrote:
Am Mittwoch, 8. Dezember 2021, 16:12:19 CET schrieb Sascha Hauer:
quoted
"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock. The clock
name "vpll" is left for compatibility to old device trees.
Can't we just say that the binding only takes the "ref" name, but
the code still allows "vpll".
I think I remember Rob suggesting something similar in the past.
I don't think that we need to keep the binding(-validation)
compatible with old devicetrees, but the kernel itself should stay
compatible.
Sounds reasonable. I'll also add a patch changing the in-tree users next
round.
Sascha
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From: Rob Herring <robh@kernel.org> Date: 2021-12-15 16:27:15
On Wed, 08 Dec 2021 16:12:18 +0100, Sascha Hauer wrote:
None of the upstream device tree files has a "unwedge" pinctrl
specified. Make it optional.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml | 1 +
1 file changed, 1 insertion(+)
From: Rob Herring <robh@kernel.org> Date: 2021-12-15 16:38:03
On Wed, Dec 08, 2021 at 04:12:22PM +0100, Sascha Hauer wrote:
quoted hunk
The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
The binding differs slightly from the existing VOP binding, so add a new
binding file for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../display/rockchip/rockchip-vop2.yaml | 118 ++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC display controller (VOP2)
+
+description:
+ VOP2 (Video Output Processor v2) is the display controller for the Rockchip
+ series of SoCs which transfers the image data from a video memory
+ buffer to an external LCD interface.
+
+maintainers:
+ - Sandy Huang [off-list ref]
+ - Heiko Stuebner [off-list ref]
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3566-vop
+ - rockchip,rk3568-vop
+
+ reg:
+ minItems: 1
+ items:
+ - description:
+ Must contain one entry corresponding to the base address and length
+ of the register space.
+ - description:
+ Can optionally contain a second entry corresponding to
+ the CRTC gamma LUT address.
+
+ interrupts:
+ maxItems: 1
+ description:
+ The VOP interrupt is shared by several interrupt sources, such as
+ frame start (VSYNC), line flag and other status interrupts.
+
+ clocks:
+ items:
+ - description: Clock for ddr buffer transfer.
+ - description: Clock for the ahb bus to R/W the phy regs.
+ - description: Pixel clock for video port 0.
+ - description: Pixel clock for video port 1.
+ - description: Pixel clock for video port 2.
+
+ clock-names:
+ items:
+ - const: aclk_vop
+ - const: hclk_vop
+ - const: dclk_vp0
+ - const: dclk_vp1
+ - const: dclk_vp2
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port