[PATCH v6 2/2] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access
From: Daniel Golle <daniel@makrotopia.org>
Date: 2021-12-28 00:09:37
Also in:
linux-mediatek, lkml, netdev
Subsystem:
mediatek ethernet driver, networking drivers, the rest · Maintainers:
Felix Fietkau, Lorenzo Bianconi, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Implement read and write access to IEEE 802.3 Clause 45 Ethernet phy registers. Tested on the Ubiquiti UniFi 6 LR access point featuring MediaTek MT7622BV WiSoC with Aquantia AQR112C. Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 56 ++++++++++++++++++--- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 ++ 2 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 72b3ae7b5ff8d..4dc1bb521ed76 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c@@ -102,10 +102,30 @@ static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, write_data &= 0xffff; - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | - (phy_reg << PHY_IAC_REG_SHIFT) | - (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, - MTK_PHY_IAC); + if (phy_reg & MII_ADDR_C45) { + u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0); + u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK); + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT) | + reg, + MTK_PHY_IAC); + + if (mtk_mdio_busy_wait(eth)) + return -EBUSY; + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT) | + write_data, + MTK_PHY_IAC); + } else { + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | + (phy_reg << PHY_IAC_REG_SHIFT) | + (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, + MTK_PHY_IAC); + } if (mtk_mdio_busy_wait(eth)) return -EBUSY;
@@ -118,10 +138,29 @@ static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) if (mtk_mdio_busy_wait(eth)) return -EBUSY; - mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | - (phy_reg << PHY_IAC_REG_SHIFT) | - (phy_addr << PHY_IAC_ADDR_SHIFT), - MTK_PHY_IAC); + if (phy_reg & MII_ADDR_C45) { + u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0); + u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK); + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT) | + reg, + MTK_PHY_IAC); + + if (mtk_mdio_busy_wait(eth)) + return -EBUSY; + + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 | + (phy_addr << PHY_IAC_ADDR_SHIFT) | + (dev_num << PHY_IAC_REG_SHIFT), + MTK_PHY_IAC); + } else { + mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | + (phy_reg << PHY_IAC_REG_SHIFT) | + (phy_addr << PHY_IAC_ADDR_SHIFT), + MTK_PHY_IAC); + } if (mtk_mdio_busy_wait(eth)) return -EBUSY;
@@ -493,6 +532,7 @@ static int mtk_mdio_init(struct mtk_eth *eth) eth->mii_bus->name = "mdio"; eth->mii_bus->read = mtk_mdio_read; eth->mii_bus->write = mtk_mdio_write; + eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; eth->mii_bus->priv = eth; eth->mii_bus->parent = eth->dev;
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 5ef70dd8b49c6..b73d8adc9d24c 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h@@ -341,9 +341,12 @@ /* PHY Indirect Access Control registers */ #define MTK_PHY_IAC 0x10004 #define PHY_IAC_ACCESS BIT(31) +#define PHY_IAC_SET_ADDR 0 #define PHY_IAC_READ BIT(19) +#define PHY_IAC_READ_C45 (BIT(18) | BIT(19)) #define PHY_IAC_WRITE BIT(18) #define PHY_IAC_START BIT(16) +#define PHY_IAC_START_C45 0 #define PHY_IAC_ADDR_SHIFT 20 #define PHY_IAC_REG_SHIFT 25 #define PHY_IAC_TIMEOUT HZ
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel