On Tue, Dec 21, 2021 at 03:16:31PM +0800, Yu Tu wrote:
The UART driver compatible with the Amlogic Meson S4 SoC on-chip, change the
UART interrupt interface function while adding IRQF_SHARED flag. And add clear
AML_UART_TX_EN bit in meson_uart_shutdown funtion.
Yu Tu (3):
tty: serial: meson: modify request_irq and free_irq
tty: serial: meson: meson_uart_shutdown omit clear AML_UART_TX_EN bit
tty: serial: meson: add UART driver compatible with S4 SoC on-chip
Link:https://patchwork.kernel.org/project/linux-amlogic/patch/20211206100200.31914-1-xianwei.zhao@amlogic.com/
What is this link for?
And why patchwork?
Please just use lore.kernel.org links for mailing list threads.
thanks,
greg k-h
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Hi Greg K-H,
Thank you very much for your reply.I'll amend it as you suggest.
On 2021/12/21 15:30, Greg Kroah-Hartman wrote:
[ EXTERNAL EMAIL ]
On Tue, Dec 21, 2021 at 03:16:31PM +0800, Yu Tu wrote:
quoted
The UART driver compatible with the Amlogic Meson S4 SoC on-chip, change the
UART interrupt interface function while adding IRQF_SHARED flag. And add clear
AML_UART_TX_EN bit in meson_uart_shutdown funtion.
Yu Tu (3):
tty: serial: meson: modify request_irq and free_irq
tty: serial: meson: meson_uart_shutdown omit clear AML_UART_TX_EN bit
tty: serial: meson: add UART driver compatible with S4 SoC on-chip
Link:https://patchwork.kernel.org/project/linux-amlogic/patch/20211206100200.31914-1-xianwei.zhao@amlogic.com/
What is this link for?
And why patchwork?
Please just use lore.kernel.org links for mailing list threads.
thanks,
greg k-h
Change request_irq to devm_request_irq and free_irq to devm_free_irq.
It's better to change the code this way.
The IRQF_SHARED interrupt flag was added because an interrupt error was
detected when the serial port was opened twice in a row on the project.
Signed-off-by: Yu Tu <redacted>
---
drivers/tty/serial/meson_uart.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
On Tue, Dec 21, 2021 at 03:16:32PM +0800, Yu Tu wrote:
Change request_irq to devm_request_irq and free_irq to devm_free_irq.
It's better to change the code this way.
Why? What did this fix up? You still are manually requesting and
freeing the irq. What bug did you fix?
The IRQF_SHARED interrupt flag was added because an interrupt error was
detected when the serial port was opened twice in a row on the project.
That is a different change. Make that a different patch.
thanks,
greg k-h
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On Tue, Dec 21, 2021 at 03:16:32PM +0800, Yu Tu wrote:
quoted
Change request_irq to devm_request_irq and free_irq to devm_free_irq.
It's better to change the code this way.
Why? What did this fix up? You still are manually requesting and
freeing the irq. What bug did you fix?
I think this is exactly what you said. It's not necessary.
quoted
The IRQF_SHARED interrupt flag was added because an interrupt error was
detected when the serial port was opened twice in a row on the project.
That is a different change. Make that a different patch.
The main purpose of this change is that I found some users in the actual
project with the following usages:
(1)open(/dev/ttyAML0);
(2)open(/dev/ttyAML0);
The open function calls the meson_uart_startup function. If this is the
case, an interrupt error is reported.So So the IRQF_SHARED flag was added.
I'm going to do this for now, remove free_irq and request_irq
function,then add devm_request_irq in meson_uart_probe function.
This solves the above problem without adding IRQF_SHARED.
The meson_uart_shutdown function should have the opposite operation to
the meson_uart_startup function, so the shutdown of AML_UART_TX_EN is
logically missing.
Signed-off-by: Yu Tu <redacted>
---
drivers/tty/serial/meson_uart.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
On Tue, Dec 21, 2021 at 03:16:33PM +0800, Yu Tu wrote:
The meson_uart_shutdown function should have the opposite operation to
the meson_uart_startup function, so the shutdown of AML_UART_TX_EN is
logically missing.
Signed-off-by: Yu Tu <redacted>
What commit does this fix? Should it go to stable kernels? Please put
that in here if needed.
thanks,
greg k-h
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On Tue, Dec 21, 2021 at 03:16:33PM +0800, Yu Tu wrote:
quoted
The meson_uart_shutdown function should have the opposite operation to
the meson_uart_startup function, so the shutdown of AML_UART_TX_EN is
logically missing.
Signed-off-by: Yu Tu <redacted>
What commit does this fix? Should it go to stable kernels? Please put
that in here if needed.
It has not yet been revealed that this is a bug. The reason I changed it
was because I thought it was an improvement and it might be a hidden
bug.The AML_UART_TX_EN bit is conspicuously missing when comparing the
meson_uart_shutdown and meson_uart_startup functions.So I think it's
best to add.
The S4 SoC on-chip UART uses a 12M clock as the clock source for
calculating the baud rate of the UART. But previously, chips used 24M or
other clock sources. So add this change. The specific clock source is
determined by chip design.
Signed-off-by: Yu Tu <redacted>
---
drivers/tty/serial/meson_uart.c | 62 +++++++++++++++++++++++++++++----
1 file changed, 55 insertions(+), 7 deletions(-)
@@ -294,16 +302,29 @@ static int meson_uart_startup(struct uart_port *port)staticvoidmeson_uart_change_speed(structuart_port*port,unsignedlongbaud){+structmeson_uart_data*uart_data=port->private_data;u32val;while(!meson_uart_tx_empty(port))cpu_relax();+val=readl_relaxed(port->membase+AML_UART_REG5);+val&=~AML_UART_BAUD_MASK;+if(port->uartclk==24000000){-val=((port->uartclk/3)/baud)-1;-val|=AML_UART_BAUD_XTAL;+if(uart_data->xtal_tick_en){+val=(port->uartclk/2+baud/2)/baud-1;+val|=(AML_UART_BAUD_XTAL|AML_UART_BAUD_XTAL_DIV2);+}else{+val=((port->uartclk/3)+baud/2)/baud-1;+val&=(~(AML_UART_BAUD_XTAL_TICK|+AML_UART_BAUD_XTAL_DIV2));+val|=AML_UART_BAUD_XTAL;+}}else{val=((port->uartclk*10/(baud*4)+5)/10)-1;+val&=(~(AML_UART_BAUD_XTAL|AML_UART_BAUD_XTAL_TICK|+AML_UART_BAUD_XTAL_DIV2));}val|=AML_UART_BAUD_USE;writel(val,port->membase+AML_UART_REG5);
@@ -714,6 +735,7 @@ static int meson_uart_probe(struct platform_device *pdev){structresource*res_mem,*res_irq;structuart_port*port;+structmeson_uart_data*uart_data;intret=0;intid=-1;
@@ -729,6 +751,10 @@ static int meson_uart_probe(struct platform_device *pdev)}}+uart_data=of_device_get_match_data(&pdev->dev);+if(!uart_data)+return-EINVAL;+if(pdev->id<0||pdev->id>=AML_UART_PORT_NUM)return-EINVAL;
@@ -770,6 +796,7 @@ static int meson_uart_probe(struct platform_device *pdev)port->x_char=0;port->ops=&meson_uart_ops;port->fifosize=64;+port->private_data=uart_data;meson_ports[pdev->id]=port;platform_set_drvdata(pdev,port);
@@ -798,14 +825,35 @@ static int meson_uart_remove(struct platform_device *pdev)return0;}+staticconststructmeson_uart_datameson_uart_data={+.xtal_tick_en=0,+};++staticconststructmeson_uart_datas4_meson_uart_data={+.xtal_tick_en=1,+};+staticconststructof_device_idmeson_uart_dt_match[]={/* Legacy bindings, should be removed when no more used */-{.compatible="amlogic,meson-uart"},+{.compatible="amlogic,meson-uart",+.data=&meson_uart_data+},/* Stable bindings */-{.compatible="amlogic,meson6-uart"},-{.compatible="amlogic,meson8-uart"},-{.compatible="amlogic,meson8b-uart"},-{.compatible="amlogic,meson-gx-uart"},+{.compatible="amlogic,meson6-uart",+.data=&meson_uart_data+},+{.compatible="amlogic,meson8-uart",+.data=&meson_uart_data+},+{.compatible="amlogic,meson8b-uart",+.data=&meson_uart_data+},+{.compatible="amlogic,meson-gx-uart",+.data=&meson_uart_data+},+{.compatible="amlogic,meson-s4-uart",+.data=&s4_meson_uart_data+},{/* sentinel */},};MODULE_DEVICE_TABLE(of,meson_uart_dt_match);
--
2.33.1
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On Tue, Dec 21, 2021 at 03:16:34PM +0800, Yu Tu wrote:
quoted hunk
The S4 SoC on-chip UART uses a 12M clock as the clock source for
calculating the baud rate of the UART. But previously, chips used 24M or
other clock sources. So add this change. The specific clock source is
determined by chip design.
Signed-off-by: Yu Tu <redacted>
---
drivers/tty/serial/meson_uart.c | 62 +++++++++++++++++++++++++++++----
1 file changed, 55 insertions(+), 7 deletions(-)
@@ -294,16 +302,29 @@ static int meson_uart_startup(struct uart_port *port) static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) {+ struct meson_uart_data *uart_data = port->private_data; u32 val; while (!meson_uart_tx_empty(port)) cpu_relax();+ val = readl_relaxed(port->membase + AML_UART_REG5);+ val &= ~AML_UART_BAUD_MASK;+ if (port->uartclk == 24000000) {- val = ((port->uartclk / 3) / baud) - 1;- val |= AML_UART_BAUD_XTAL;+ if (uart_data->xtal_tick_en) {+ val = (port->uartclk / 2 + baud / 2) / baud - 1;+ val |= (AML_UART_BAUD_XTAL | AML_UART_BAUD_XTAL_DIV2);+ } else {+ val = ((port->uartclk / 3) + baud / 2) / baud - 1;+ val &= (~(AML_UART_BAUD_XTAL_TICK |+ AML_UART_BAUD_XTAL_DIV2));+ val |= AML_UART_BAUD_XTAL;+ } } else { val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;+ val &= (~(AML_UART_BAUD_XTAL | AML_UART_BAUD_XTAL_TICK |+ AML_UART_BAUD_XTAL_DIV2)); } val |= AML_UART_BAUD_USE; writel(val, port->membase + AML_UART_REG5);
@@ -714,6 +735,7 @@ static int meson_uart_probe(struct platform_device *pdev) { struct resource *res_mem, *res_irq; struct uart_port *port;+ struct meson_uart_data *uart_data; int ret = 0; int id = -1;
@@ -729,6 +751,10 @@ static int meson_uart_probe(struct platform_device *pdev) } }+ uart_data = of_device_get_match_data(&pdev->dev);+ if (!uart_data)+ return -EINVAL;
Wrong spacing.
Always use checkpatch.pl on your patches before sending them out.
And did you just break existing systems? Do you know if all older ones
will still work with that call?
As your whole structure just has one bit, why not just use that as the
data value, instead of a structure? No need to be complex here at all.
thanks,
greg k-h
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On Tue, Dec 21, 2021 at 03:16:34PM +0800, Yu Tu wrote:
quoted
The S4 SoC on-chip UART uses a 12M clock as the clock source for
calculating the baud rate of the UART. But previously, chips used 24M or
other clock sources. So add this change. The specific clock source is
determined by chip design.
Signed-off-by: Yu Tu <redacted>
---
drivers/tty/serial/meson_uart.c | 62 +++++++++++++++++++++++++++++----
1 file changed, 55 insertions(+), 7 deletions(-)
@@ -294,16 +302,29 @@ static int meson_uart_startup(struct uart_port *port) static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) {+ struct meson_uart_data *uart_data = port->private_data; u32 val; while (!meson_uart_tx_empty(port)) cpu_relax();+ val = readl_relaxed(port->membase + AML_UART_REG5);+ val &= ~AML_UART_BAUD_MASK;+ if (port->uartclk == 24000000) {- val = ((port->uartclk / 3) / baud) - 1;- val |= AML_UART_BAUD_XTAL;+ if (uart_data->xtal_tick_en) {+ val = (port->uartclk / 2 + baud / 2) / baud - 1;+ val |= (AML_UART_BAUD_XTAL | AML_UART_BAUD_XTAL_DIV2);+ } else {+ val = ((port->uartclk / 3) + baud / 2) / baud - 1;+ val &= (~(AML_UART_BAUD_XTAL_TICK |+ AML_UART_BAUD_XTAL_DIV2));+ val |= AML_UART_BAUD_XTAL;+ } } else { val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1;+ val &= (~(AML_UART_BAUD_XTAL | AML_UART_BAUD_XTAL_TICK |+ AML_UART_BAUD_XTAL_DIV2)); } val |= AML_UART_BAUD_USE; writel(val, port->membase + AML_UART_REG5);
@@ -714,6 +735,7 @@ static int meson_uart_probe(struct platform_device *pdev) { struct resource *res_mem, *res_irq; struct uart_port *port;+ struct meson_uart_data *uart_data; int ret = 0; int id = -1;
@@ -729,6 +751,10 @@ static int meson_uart_probe(struct platform_device *pdev) } }+ uart_data = of_device_get_match_data(&pdev->dev);+ if (!uart_data)+ return -EINVAL;
Wrong spacing.
Always use checkpatch.pl on your patches before sending them out.
Sorry, this is a rookie mistake.But I did check it locally before
sending it. I will follow your advice strictly later.
And did you just break existing systems? Do you know if all older ones
will still work with that call?
It does affect older systems, but the new and older baud rates are not
the same. I checked the documents before I made any changes. So this
change is compatible with the older.
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: 2021-12-24 17:25:36
Hello,
On Tue, Dec 21, 2021 at 8:17 AM Yu Tu [off-list ref] wrote:
The S4 SoC on-chip UART uses a 12M clock as the clock source for
calculating the baud rate of the UART. But previously, chips used 24M or
other clock sources. So add this change. The specific clock source is
determined by chip design.
Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL?
If there's still a 24MHz XTAL then I think this description is not
correct - at least based on how I understand the UART controller.
SoCs up to GXL and GXM had an internal divide-by-3 (clock divider) in
the UART controller IP and an external 24MHz XTAL.
This was not configurable, so the clock for all baud-rates had to be
derived from an 8MHz (24MHz divided by 3) clock.
With the A311D (G12B, which is still using an external 24MHz XTAL) SoC
the UART controller gained two new bits - with configurable dividers -
according to the public datasheets:
UART_EE_A_REG5[26]:
- 0x0: divide the input clock by 3 (meaning: this internally works
with an 8MHz clock)
- 0x1: use the input clock directly without further division (meaning:
this internally work with an 24MHz clock)
UART_EE_A_REG5[27]:
- 0x0: use the clock as configured in UART_EE_A_REG5[26]
- 0x1: divide the input clock by 2 (meaning: this internally works
with an 12MHz clock)
While writing this email I did some investigation and found that
UART_EE_A_REG5[26] is used in the vendor kernel even for GXL and GXM
SoCs.
So this probably has been introduced with the GXL generation (and thus
is missing on GXBB and earlier SoCs).
Also UART_EE_A_REG5[27] seems to have been introduced with the G12A
generation of SoCs (not surprising since G12A and G12B peripherals are
very similar).
Does the UART controller not work with divide-by-3 (as we have it
today) or are these configurable dividers to reduce jitter?
Best regards,
Martin
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Hi Martin,
Thank you very much for your reply.
On 2021/12/25 1:25, Martin Blumenstingl wrote:
[ EXTERNAL EMAIL ]
Hello,
On Tue, Dec 21, 2021 at 8:17 AM Yu Tu [off-list ref] wrote:
quoted
The S4 SoC on-chip UART uses a 12M clock as the clock source for
calculating the baud rate of the UART. But previously, chips used 24M or
other clock sources. So add this change. The specific clock source is
determined by chip design.
Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL?
If there's still a 24MHz XTAL then I think this description is not
correct - at least based on how I understand the UART controller.
The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode).
This register description is the same as the G12A and G12B you know.
SoCs up to GXL and GXM had an internal divide-by-3 (clock divider) in
the UART controller IP and an external 24MHz XTAL.
This was not configurable, so the clock for all baud-rates had to be
derived from an 8MHz (24MHz divided by 3) clock.
With the A311D (G12B, which is still using an external 24MHz XTAL) SoC
the UART controller gained two new bits - with configurable dividers -
according to the public datasheets:
UART_EE_A_REG5[26]:
- 0x0: divide the input clock by 3 (meaning: this internally works
with an 8MHz clock)
- 0x1: use the input clock directly without further division (meaning:
this internally work with an 24MHz clock)
UART_EE_A_REG5[27]:
- 0x0: use the clock as configured in UART_EE_A_REG5[26]
- 0x1: divide the input clock by 2 (meaning: this internally works
with an 12MHz clock)
While writing this email I did some investigation and found that
UART_EE_A_REG5[26] is used in the vendor kernel even for GXL and GXM
SoCs.
So this probably has been introduced with the GXL generation (and thus
is missing on GXBB and earlier SoCs).
Also UART_EE_A_REG5[27] seems to have been introduced with the G12A
generation of SoCs (not surprising since G12A and G12B peripherals are
very similar).
Does the UART controller not work with divide-by-3 (as we have it
today) or are these configurable dividers to reduce jitter?
The UART controller can work with divide-by-3.
The chip history as you described above, the current reason for using
12MHz clock is really what you call reduce jitter. The UART mainly
connects to Bluetooth and uses typical baud rates of 2Mhz, 3MHz and
4MHz, so 12MHz is used as the clock source.
On Mon 27 Dec 2021 at 14:56, Yu Tu [off-list ref] wrote:
Hi Martin,
Thank you very much for your reply.
On 2021/12/25 1:25, Martin Blumenstingl wrote:
quoted
[ EXTERNAL EMAIL ]
Hello,
On Tue, Dec 21, 2021 at 8:17 AM Yu Tu [off-list ref] wrote:
quoted
The S4 SoC on-chip UART uses a 12M clock as the clock source for
calculating the baud rate of the UART. But previously, chips used 24M or
other clock sources. So add this change. The specific clock source is
determined by chip design.
Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL?
If there's still a 24MHz XTAL then I think this description is not
correct - at least based on how I understand the UART controller.
The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in
romcode). This register description is the same as the G12A and G12B you
know.
quoted
SoCs up to GXL and GXM had an internal divide-by-3 (clock divider) in
the UART controller IP and an external 24MHz XTAL.
This was not configurable, so the clock for all baud-rates had to be
derived from an 8MHz (24MHz divided by 3) clock.
With the A311D (G12B, which is still using an external 24MHz XTAL) SoC
the UART controller gained two new bits - with configurable dividers -
according to the public datasheets:
UART_EE_A_REG5[26]:
- 0x0: divide the input clock by 3 (meaning: this internally works
with an 8MHz clock)
- 0x1: use the input clock directly without further division (meaning:
this internally work with an 24MHz clock)
UART_EE_A_REG5[27]:
- 0x0: use the clock as configured in UART_EE_A_REG5[26]
- 0x1: divide the input clock by 2 (meaning: this internally works
with an 12MHz clock)
While writing this email I did some investigation and found that
UART_EE_A_REG5[26] is used in the vendor kernel even for GXL and GXM
SoCs.
So this probably has been introduced with the GXL generation (and thus
is missing on GXBB and earlier SoCs).
Also UART_EE_A_REG5[27] seems to have been introduced with the G12A
generation of SoCs (not surprising since G12A and G12B peripherals are
very similar).
Does the UART controller not work with divide-by-3 (as we have it
today) or are these configurable dividers to reduce jitter?
The UART controller can work with divide-by-3.
The chip history as you described above, the current reason for using 12MHz
clock is really what you call reduce jitter. The UART mainly connects to
Bluetooth and uses typical baud rates of 2Mhz, 3MHz and 4MHz, so 12MHz is
used as the clock source.
Looks to me that the clock divider above should be modelled properly
with CCF. If you wish the initial Romcode setting to remain untouched,
then don't put CLK_SET_RATE_PARENT to stop rate propagation.
CCF will figure out what the internal rate is. You don't need to device
tree data if things are done properly
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: 2021-12-27 20:04:30
Hello,
On Mon, Dec 27, 2021 at 7:56 AM Yu Tu [off-list ref] wrote:
[...]
quoted
Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL?
If there's still a 24MHz XTAL then I think this description is not
correct - at least based on how I understand the UART controller.
The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode).
This register description is the same as the G12A and G12B you know.
Thank you for this explanation!
So the problem is that we're not touching bit 26 and bit 27 - and with
the updated romcode you would not get any serial output since the
divider is calculated off the wrong clock.
I agree with Jerome that we shouldn't put a flag in device-tree.
Also I did some experimenting with Jerome's idea to implement the
clocks using CCF (common clock framework), see the attached patches.
It was a bit tricky because some initial clean-ups were needed in the
serial driver.
Note: I have only briefly tested this on a 32-bit Meson8m2 SoC, see my
attached patches and the clk_summary debugfs output.
In fact, I expect that there are some issues with at least one of the
patches as the whole bit 26 and bit 27 code is untested.
Do you see any problems with this patch?
Could you try to implement CCF support with the idea from the attached
patches (you don't need to re-use them, I just wrote them to make it
clearer in our discussion what we're talking about).
Best regards,
Martin
Hi Martin and Jerome，
Thank you very much for your reply. I have learned a lot from your
communication.
On 2021/12/28 4:04, Martin Blumenstingl wrote:
[ EXTERNAL EMAIL ]
Hello,
On Mon, Dec 27, 2021 at 7:56 AM Yu Tu [off-list ref] wrote:
[...]
quoted
quoted
Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL?
If there's still a 24MHz XTAL then I think this description is not
correct - at least based on how I understand the UART controller.
The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in romcode).
This register description is the same as the G12A and G12B you know.
Thank you for this explanation!
So the problem is that we're not touching bit 26 and bit 27 - and with
the updated romcode you would not get any serial output since the
divider is calculated off the wrong clock.
I agree with Jerome that we shouldn't put a flag in device-tree.
Also I did some experimenting with Jerome's idea to implement the
clocks using CCF (common clock framework), see the attached patches.
It was a bit tricky because some initial clean-ups were needed in the
serial driver.
Note: I have only briefly tested this on a 32-bit Meson8m2 SoC, see my
attached patches and the clk_summary debugfs output.
In fact, I expect that there are some issues with at least one of the
patches as the whole bit 26 and bit 27 code is untested.
Do you see any problems with this patch?
Could you try to implement CCF support with the idea from the attached
patches (you don't need to re-use them, I just wrote them to make it
clearer in our discussion what we're talking about).
I couldn't agree with you more. I have verified it on a 64-bit S4
platform. Please refer to the attachment for verification output
information.
I will prepare the second version of patch according to the example
ideas you provided.