On Fri, Dec 17, 2021 at 07:03:45PM +0000, Sudeep Holla wrote:

On Fri, Dec 17, 2021 at 12:14:22PM -0600, Rob Herring wrote:

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On Fri, Dec 17, 2021 at 10:57 AM Robin Murphy [off-list ref] wrote:

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Hi Rob,

On 2021-12-16 23:31, Rob Herring wrote:

quoted

Use the minimum CPU h/w id of the CPUs associated with the cache for the
cache 'id'. This will provide a stable id value for a given system. As

I am trying to follow the code. IIUC, the level one(I$ and D$) are skipped
in this logic and the private unified cache if any will get the cpu hwid as
the cache id which is all fine. But what happens if there are 2 levels of
unified private cache ? I am assuming we only care about shared caches for
MPAM and ignore private caches which sounds OK but I just wanted to confirm.

quoted

quoted

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we need to check all possible CPUs, we can't use the shared_cpu_map
which is just online CPUs. There's not a cache to CPUs mapping in DT, so
we have to walk all CPU nodes and then walk cache levels.

I would have preferred to add the cache IDs in DT similar to ACPI but I see
you have certain concerns with that which are valid as well.

One thing I forgot to add is for some weird reasons, some platform supports
both DT and ACPI, this will force the ID generated here to be used in ACPI as
well to ensure same userspace scripts can be used to manage both. That doesn't
sound so great to me.

-- 
Regards,
Sudeep

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