Hi Daniel,

What do you think about the following description ?  :  "
    clocksource: msc313e: Add support for ssd20xd-based platforms

    On SSD20X family SoCs bootrom sets the divider for timer0 to run at
    12Mhz, while timer1 and timer2 are kept unchanged and defaut to ~432Mhz.
    There are no ways to reduce or divide these clocks in the clktree.
    However, These SoCs provide an internal "timer_divide" register that can
    act on this input clock. This commit adds support for this register,
    as timer1 and timer2 are used as clockevents these will run at 48Mhz.

    Signed-off-by: Romain Perier [off-list ref]
"

Romain

Le mer. 15 déc. 2021 à 13:00, Daniel Palmer [off-list ref] a écrit :

Hi Romain,

On Mon, 13 Dec 2021 at 03:19, Romain Perier [off-list ref] wrote:

quoted

SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and
timer2, while timer0 is running at 12Mhz.

I don't think this is technically true. I think the boot rom sets the
divider for timer0 so that it runs at ~12MHz.
I think the current change to only configure timer1 and timer2 is ok
but maybe the commit message should say that timer0 is configured to
be backwards compatible at boot.

Cheers,

Daniel

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