Hi Heiko, Yifeng,

Could you advise whether we should change the DT layout and driver a bit.
Some properties don't really fit to one particular phy node, so move
them to a parent node.

Maybe replace rockchip,sgmii-mac-sel by a node in phy 1 and 2 ??

Also there are two USB3.0 Controllers, one can use as USB3.0 OTG
Controller, another one can use as USB3.0 Host Controller only.
Yet properties are called: rockchip,dis-u3otg0-port,
rockchip,dis-u3otg1-port.
Maybe replace them by a node ??

Unknown capabilities of future (rk3588) Naneng versions (combined  host
and otg ??)

Maybe follow more in line with the phy-rockchip-inno-usb2.c and
phy-rockchip-usb.c drivers.

Could you confirm combo PHY on the RK3566 lacks the QSGMII/SGMII stuff?
(Lack of rk3566 TRM)

With so many differences maybe use separate compatible string and keep
the DT nodes completely apart.
(rockchip,rk3566-naneng-combphy, rockchip,rk3568-naneng-combphy)



Johan

================================

	combphy: combphy {
		compatible = "rockchip,rk3568-naneng-combphy";
========
		rockchip,ext-refclk;
		rockchip,enable-ssc;
		rockchip,pipe-grf = <&pipegrf>;
========
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		combphy0: combi-phy@fe820000 {
			reg = <0x0 0xfe820000 0x0 0x100>;
			clocks = <&pmucru CLK_PCIEPHY0_REF>,
				 <&cru PCLK_PIPEPHY0>,
				 <&cru PCLK_PIPE>;
			clock-names = "ref", "apb", "pipe";
			assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
			assigned-clock-rates = <100000000>;
			resets = <&cru SRST_PIPEPHY0>;
			rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
			#phy-cells = <1>;
			status = "disabled";

			u3phy0_otg: otg-port {
===
				/* ??? */
				#phy-cells = <0>;
				status = "disabled";
===
			};
		};

		combphy1: combi-phy@fe830000 {
			reg = <0x0 0xfe830000 0x0 0x100>;
			clocks = <&pmucru CLK_PCIEPHY1_REF>,
				 <&cru PCLK_PIPEPHY1>,
				 <&cru PCLK_PIPE>;
			clock-names = "ref", "apb", "pipe";
			assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
			assigned-clock-rates = <100000000>;
			resets = <&cru SRST_PIPEPHY1>;
			rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
			#phy-cells = <1>;
			status = "disabled";

			u3phy0_host: host-port {
===
				/* ??? */
				#phy-cells = <0>;
				status = "disabled";
===
			}

			sgmii_port: sgmii-port {

				/* ??? */
				status = "disabled";
			}
		};

		combphy2: combi-phy@fe840000 {
			reg = <0x0 0xfe840000 0x0 0x100>;
			clocks = <&pmucru CLK_PCIEPHY2_REF>,
				 <&cru PCLK_PIPEPHY2>,
				 <&cru PCLK_PIPE>;
			clock-names = "ref", "apb", "pipe";
			assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
			assigned-clock-rates = <100000000>;
			resets = <&cru SRST_PIPEPHY2>;
			rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
			#phy-cells = <1>;
			status = "disabled";

			sgmii_port: sgmii-port {

				/* ??? */
				status = "disabled";
			}
		};
	}

==============
Example from phy-rockchip-usb.c:

	for_each_available_child_of_node(dev->of_node, child) {
		err = rockchip_combphy_init(phy_base, child);
		if (err) {
			of_node_put(child);
			return err;
		}
	}

==============
Example from phy-rockchip-inno-usb2.c:

		/* initialize otg/host port separately */
		if (of_node_name_eq(child_np, "host-port")) {
			ret = rockchip_usb3phy_host_port_init(rphy, rport,
							      child_np);
			if (ret)
				goto put_child;
		} else {
			ret = rockchip_usb3phy_otg_port_init(rphy, rport,
							     child_np);
			if (ret)
				goto put_child;
		}

===============
Example from dwmac-rk.c:
	/* Multiple Naneng phy controllers need
	 * to be distinguished.
	 */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res) {
		int i = 0;

		while (ops->regs[i]) {
			if (ops->regs[i] == res->start) {
				bsp_priv->id = i;
				break;
			}
			i++;
		}
	}

================

On 12/15/21 10:56 AM, Yifeng Zhao wrote:

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