Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins)
The hwirq base for each sgpio bank should be multiples of 64 rather than
multiples of 32.

This patch series contains a patch for fixing wrong hwirq base in
irq handler.

Please help to review.

Steven Lee (1):
  gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler

 drivers/gpio/gpio-aspeed-sgpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.1


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