Re: [PATCH 1/2] ARM: dts: at91: sama7g5: Add QSPI nodes
From: Nicolas Ferre <nicolas.ferre@microchip.com>
Date: 2021-12-13 13:59:10
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On 09/12/2021 at 13:36, Tudor Ambarus wrote:
sama7g5 embedds 2 instances of QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.
Signed-off-by: Tudor Ambarus <redacted>Looks good to me: integrated in at91-dt for 5.17. Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Best regards, Nicolas
quoted hunk ↗ jump to hunk
--- arch/arm/boot/dts/sama7g5.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7039311bf678..eddcfbf4d223 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi@@ -181,6 +181,36 @@ tcb1: timer@e0800000 { clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + qspi0: spi@e080c000 { + compatible = "microchip,sama7g5-ospi"; + reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, + <&dma0 AT91_XDMAC_DT_PERID(40)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@e0810000 { + compatible = "microchip,sama7g5-qspi"; + reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, + <&dma0 AT91_XDMAC_DT_PERID(42)>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; + clock-names = "pclk", "gclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>;
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