Re: [v1 3/5] arm64: dts: mediatek: Correct SPI clock of MT8192
From: Nícolas F. R. A. Prado <hidden>
Date: 2021-12-06 16:47:17
Also in:
linux-devicetree, linux-mediatek, lkml
Hi, On Wed, Aug 25, 2021 at 09:11:18AM +0800, Chun-Jie Chen wrote:
update uart0 ~ 7 clocks to the real ones.
Same comment from patch 1. But also here you had a typo: should be spi instead of uart. Reviewed-by: Nícolas F. R. A. Prado <redacted> Thanks, Nícolas
quoted hunk ↗ jump to hunk
Signed-off-by: Chun-Jie Chen <redacted> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++------------ 1 file changed, 24 insertions(+), 24 deletions(-)diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 31d135e18784..d1c85d3e152b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi@@ -355,9 +355,9 @@ #size-cells = <0>; reg = <0 0x1100a000 0 0x1000>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };@@ -369,9 +369,9 @@ #size-cells = <0>; reg = <0 0x11010000 0 0x1000>; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI1>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };@@ -383,9 +383,9 @@ #size-cells = <0>; reg = <0 0x11012000 0 0x1000>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };@@ -397,9 +397,9 @@ #size-cells = <0>; reg = <0 0x11013000 0 0x1000>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI3>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };@@ -411,9 +411,9 @@ #size-cells = <0>; reg = <0 0x11018000 0 0x1000>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI4>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };@@ -425,9 +425,9 @@ #size-cells = <0>; reg = <0 0x11019000 0 0x1000>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI5>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };@@ -439,9 +439,9 @@ #size-cells = <0>; reg = <0 0x1101d000 0 0x1000>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI6>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };@@ -453,9 +453,9 @@ #size-cells = <0>; reg = <0 0x1101e000 0 0x1000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI7>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; };-- 2.18.0
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