Re: [PATCH v3] PCI: mediatek-gen3: Disable DVFSRC voltage request

Hi Maintainers,

Just gentle ping for this patch, is there anything I need to do to get
this patch merged?

Thanks.

On Tue, 2021-11-09 at 14:10 +0800, Jianjun Wang wrote:

On Fri, 2021-10-15 at 14:36 +0800, Jianjun Wang wrote:

quoted

When the DVFSRC (dynamic voltage and frequency scaling resource
collector)
feature is not implemented, the PCIe hardware will assert a voltage
request
signal when exit from the L1 PM Substates to request a specific
Vcore
voltage, but cannot receive the voltage ready signal, which will
cause
the link to fail to exit the L1 PM Substates.

Disable DVFSRC voltage request by default, we need to find a common
way to
enable it in the future.

Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver
for MT8192")
Signed-off-by: Jianjun Wang <redacted>
Reviewed-by: Tzung-Bi Shih <redacted>
Tested-by: Qizhong Cheng <redacted>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c

b/drivers/pci/controller/pcie-mediatek-gen3.c
index f3aeb8d4eaca..79fb12fca6a9 100644

--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c

@@ -79,6 +79,9 @@
 #define PCIE_ICMD_PM_REG		0x198
 #define PCIE_TURN_OFF_LINK		BIT(4)
 
+#define PCIE_MISC_CTRL_REG		0x348
+#define PCIE_DISABLE_DVFSRC_VLT_REQ	BIT(1)
+
 #define PCIE_TRANS_TABLE_BASE_REG	0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET	0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET	0x8

@@ -297,6 +300,11 @@ static int mtk_pcie_startup_port(struct

mtk_pcie_port *port)
 	val &= ~PCIE_INTX_ENABLE;
 	writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
 
+	/* Disable DVFSRC voltage request */
+	val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG);
+	val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
+	writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG);
+
 	/* Assert all reset signals */
 	val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
 	val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
PCIE_PE_RSTB;

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