Re: [PATCH v5 10/15] clk: at91: clk-master: fix prescaler logic
From: Nicolas Ferre <nicolas.ferre@microchip.com>
Date: 2021-10-15 07:58:40
Also in:
linux-clk, lkml
On 11/10/2021 at 13:27, Claudiu Beznea wrote:
When prescaler value read from register is MASTER_PRES_MAX it means
that the input clock will be divided by 3. Fix the code to reflect
this.
Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
Signed-off-by: Claudiu Beznea <redacted>Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
quoted hunk ↗ jump to hunk
--- drivers/clk/at91/clk-master.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 6da9ae34313a..e67bcd03a827 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, val &= master->layout->mask; pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; - if (pres == 3 && characteristics->have_div3_pres) + if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) pres = 3; else pres = (1 << pres);
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