Re: [PATCH 3/4] arm64: dts: marvell: espressobin-ultra: add PHY and switch reset pins
From: Pali Rohár <pali@kernel.org>
Date: 2021-09-28 15:32:56
Also in:
linux-devicetree, lkml
On Monday 27 September 2021 17:41:58 Robert Marko wrote:
Both the Topaz switch and 88E1512 PHY have their reset and interrupts connected to the SoC. So, define the Topaz and 88E1512 reset pins in the DTS.
Are reset pins connected only on ultra variant? Or on all espressobin variants? Because if they are on all variants then definitions should go into common dtsi file. I see that "gpionb 2" is on v7 variant connected to LED2. So I'm not sure if this one gpio is also shared or not.
Defining the interrupt pins wont work as both the 88E1512 and the Topaz switch uses active LOW IRQ signals but the A37xx GPIO controller only supports edge triggers. 88E1512 would require special setup anyway as its INT pin is shared with the LED2 and you first need to configure it as INT.
Do you plan to finish also this additional setup?
quoted hunk ↗ jump to hunk
Signed-off-by: Robert Marko <robert.marko@sartura.hr> --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 4 ++++ 1 file changed, 4 insertions(+)diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 8a700afd0570..96855a10b4a0 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts@@ -118,12 +118,16 @@ &usb3 { &mdio { extphy: ethernet-phy@1 { reg = <1>; + + reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; }; }; &switch0 { reg = <3>; + reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; + ports { switch0port1: port@1 { reg = <1>;-- 2.31.1
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