Thread (13 messages) 13 messages, 5 authors, 2021-10-04
STALE1714d LANDED

[PATCH 2/4] dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI

From: Sai Krishna Potthuri <hidden>
Date: 2021-09-24 10:10:04
Also in: linux-devicetree, linux-spi, lkml
Subsystem: open firmware and flattened device tree bindings, spi subsystem, the rest · Maintainers: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Mark Brown, Linus Torvalds

Add new compatible to support Cadence Octal SPI(OSPI) controller on
Xilinx Versal SoCs, also add power-domains property to the properties
list and marked as required for Xilinx Versal OSPI compatible.

Signed-off-by: Sai Krishna Potthuri <redacted>
---
 .../devicetree/bindings/spi/cdns,qspi-nor.yaml       | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index 0e7087cc8bf9..ca155abbda7a 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -11,6 +11,14 @@ maintainers:
 
 allOf:
   - $ref: spi-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: xlnx,versal-ospi-1.0
+    then:
+      required:
+        - power-domains
 
 properties:
   compatible:
@@ -20,6 +28,7 @@ properties:
               - ti,k2g-qspi
               - ti,am654-ospi
               - intel,lgm-qspi
+              - xlnx,versal-ospi-1.0
           - const: cdns,qspi-nor
       - const: cdns,qspi-nor
 
@@ -65,6 +74,9 @@ properties:
       data rather than the QSPI clock. Make sure that QSPI return clock
       is populated on the board before using this property.
 
+  power-domains:
+    maxItems: 1
+
   resets:
     maxItems: 2
 
-- 
2.17.1


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