v6:
Add the judgment condition, clear the handshake signal between dma and
i2c when multiple msgs are transmitted.
v5:
1. Replace the previous variable name "default_timing_adjust" with "use-default-timing"
2. Added waiting for dma reset mechanism
3. Remove received patch(dt-bindings: i2c: update bindings for MT8195 SOC)
v4:
1. Remove the repeated assignment of the inter_clk_div parameter
2. Modify the wrong assignment of OFFSET_MULTI_DMA
3. Unify the log print format of the i2c_dump_register() and drop the extra outer parentheses
4. Place the fixes at the very least
5. Add fixed tags 25708278f810 ("i2c: mediatek: Add i2c support for MediaTek MT8183")
6. Add "i2c: mediatek: modify bus speed calculation formula"
7. Fix single line characters exceeding 80 characters
8. Combine two different series of patches.
v3:
1. Fix code errors caused by v2 modification
v2:
1. Add "dt-bindings: i2c: add attribute default-timing-adjust"
2. Split the fix into sepatate patch.
Kewei Xu (7):
i2c: mediatek: fixing the incorrect register offset
i2c: mediatek: Reset the handshake signal between i2c and dma
i2c: mediatek: Dump i2c/dma register when a timeout occurs
dt-bindings: i2c: add attribute use-default-timing
i2c: mediatek: Add OFFSET_EXT_CONF setting back
i2c: mediatek: Isolate speed setting via dts for special devices
i2c: mediatek: modify bus speed calculation formula
.../devicetree/bindings/i2c/i2c-mt65xx.txt | 2 +
drivers/i2c/busses/i2c-mt65xx.c | 207 ++++++++++++++++--
2 files changed, 192 insertions(+), 17 deletions(-)
--
2.18.0
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The reason for the modification here is that the previous
offset information is incorrect, OFFSET_DEBUGSTAT = 0xE4 is
the correct value.
Fixes: 25708278f810 ("i2c: mediatek: Add i2c support for MediaTek MT8183")
Signed-off-by: Kewei Xu <redacted>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Due to changes in the hardware design of the handshaking signal
between i2c and dma, it is necessary to reset the handshaking
signal before each transfer to ensure that the multi-msgs can
be transferred correctly.
Signed-off-by: Kewei Xu <redacted>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
When a timeout error occurs in i2c transter, it is usually related
to the i2c/dma IP hardware configuration. Therefore, the purpose of
this patch is to dump the key register values of i2c/dma when a
timeout occurs in i2c for debugging.
Signed-off-by: Kewei Xu <redacted>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 56 ++++++++++++++++++++++++++++++++-
1 file changed, 55 insertions(+), 1 deletion(-)
@@ -550,6 +558,7 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)OFFSET_HS_STA_STO_AC_TIMING);}}+mtk_i2c_writew(i2c,ext_conf_val,OFFSET_EXT_CONF);/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */if(i2c->have_pmic)
--
2.25.1
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@@ -34,6 +34,8 @@ Optional properties: Only mt6589 and mt8135 support this feature. - mediatek,use-push-pull: IO config use push-pull mode. - vbus-supply: phandle to the regulator that provides power to SCL/SDA.+ - mediatek,use-default-timing: use default timing calculation, no timing+ adjustment. Example:
--
2.25.1
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In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust
support"), the I2C timing calculation has been revised to support
ac-timing adjustment, however that will break on some I2C components.
As a result we want to introduce a new setting "default-adjust-timing"
so those components can choose to use the old (default) timing algorithm.
Fixes: be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support")
Signed-off-by: Kewei Xu <redacted>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 77 +++++++++++++++++++++++++++++++--
1 file changed, 73 insertions(+), 4 deletions(-)
@@ -615,7 +621,7 @@ static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,unsignedintsample_ns=div_u64(1000000000ULL*(sample_cnt+1),clk_src);-if(!i2c->dev_comp->timing_adjust)+if(i2c->use_default_timing||!i2c->dev_comp->timing_adjust)return0;if(i2c->dev_comp->ltiming_adjust)
@@ -775,7 +781,65 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,return0;}-staticintmtk_i2c_set_speed(structmtk_i2c*i2c,unsignedintparent_clk)+staticintmtk_i2c_set_speed_default_timing(structmtk_i2c*i2c,+unsignedintparent_clk)+{+unsignedintclk_src;+unsignedintstep_cnt;+unsignedintsample_cnt;+unsignedintl_step_cnt;+unsignedintl_sample_cnt;+unsignedinttarget_speed;+intret;++if(i2c->dev_comp->timing_adjust)+i2c->clk_src_div*=I2C_DEFAULT_CLK_DIV;++clk_src=parent_clk/i2c->clk_src_div;+target_speed=i2c->speed_hz;++if(target_speed>I2C_MAX_FAST_MODE_PLUS_FREQ){+/* Set master code speed register */+ret=mtk_i2c_calculate_speed(i2c,clk_src,+I2C_MAX_FAST_MODE_FREQ,+&l_step_cnt,&l_sample_cnt);+if(ret<0)+returnret;++i2c->timing_reg=(l_sample_cnt<<8)|l_step_cnt;++/* Set the high speed mode register */+ret=mtk_i2c_calculate_speed(i2c,clk_src,target_speed,+&step_cnt,&sample_cnt);+if(ret<0)+returnret;++i2c->high_speed_reg=I2C_TIME_DEFAULT_VALUE|+(sample_cnt<<12)|(step_cnt<<8);++if(i2c->dev_comp->ltiming_adjust)+i2c->ltiming_reg=(l_sample_cnt<<6)|l_step_cnt|+(sample_cnt<<12)|(step_cnt<<9);+}else{+ret=mtk_i2c_calculate_speed(i2c,clk_src,target_speed,+&step_cnt,&sample_cnt);+if(ret<0)+returnret;++i2c->timing_reg=(sample_cnt<<8)|step_cnt;++/* Disable the high speed transaction */+i2c->high_speed_reg=I2C_TIME_CLR_VALUE;++if(i2c->dev_comp->ltiming_adjust)+i2c->ltiming_reg=(sample_cnt<<6)|step_cnt;+}++return0;+}++staticintmtk_i2c_set_speed_adjust_timing(structmtk_i2c*i2c,+unsignedintparent_clk){unsignedintclk_src;unsignedintstep_cnt;
@@ -1357,7 +1423,10 @@ static int mtk_i2c_probe(struct platform_device *pdev)strlcpy(i2c->adap.name,I2C_DRV_NAME,sizeof(i2c->adap.name));-ret=mtk_i2c_set_speed(i2c,clk_get_rate(clk));+if(i2c->use_default_timing)+ret=mtk_i2c_set_speed_default_timing(i2c,clk_get_rate(clk));+else+ret=mtk_i2c_set_speed_adjust_timing(i2c,clk_get_rate(clk));if(ret){dev_err(&pdev->dev,"Failed to set the speed.\n");return-EINVAL;
--
2.25.1
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When clock-div is 0 or greater than 1, the bus speed
calculated by the old speed calculation formula will be
larger than the target speed. So we update the formula.
Signed-off-by: Kewei Xu <redacted>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
---
drivers/i2c/busses/i2c-mt65xx.c | 35 +++++++++++++++++++++++----------
1 file changed, 25 insertions(+), 10 deletions(-)
@@ -725,14 +726,26 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,unsignedintbest_mul;unsignedintcnt_mul;intret=-EINVAL;+intclock_div_constraint=0;if(target_speed>I2C_MAX_HIGH_SPEED_MODE_FREQ)target_speed=I2C_MAX_HIGH_SPEED_MODE_FREQ;+if(i2c->use_default_timing){+clock_div_constraint=0;+}elseif(i2c->dev_comp->ltiming_adjust&&+i2c->ac_timing.inter_clk_div>1){+clock_div_constraint=1;+}elseif(i2c->dev_comp->ltiming_adjust&&+i2c->ac_timing.inter_clk_div==0){+clock_div_constraint=-1;+}+max_step_cnt=mtk_i2c_max_step_cnt(target_speed);base_step_cnt=max_step_cnt;/* Find the best combination */-opt_div=DIV_ROUND_UP(clk_src>>1,target_speed);+opt_div=DIV_ROUND_UP(clk_src>>1,target_speed)++clock_div_constraint;best_mul=MAX_SAMPLE_CNT_DIV*max_step_cnt;/* Search for the best pair (sample_cnt, step_cnt) with
@@ -767,7 +780,8 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,sample_cnt=base_sample_cnt;step_cnt=base_step_cnt;-if((clk_src/(2*sample_cnt*step_cnt))>target_speed){+if((clk_src/(2*(sample_cnt*step_cnt-clock_div_constraint)))>+target_speed){/* In this case, hardware can't support such*lowi2c_bus_freq*/
@@ -854,13 +868,16 @@ static int mtk_i2c_set_speed_adjust_timing(struct mtk_i2c *i2c,target_speed=i2c->speed_hz;parent_clk/=i2c->clk_src_div;-if(i2c->dev_comp->timing_adjust)-max_clk_div=MAX_CLOCK_DIV;+if(i2c->dev_comp->timing_adjust&&i2c->dev_comp->ltiming_adjust)+max_clk_div=MAX_CLOCK_DIV_5BITS;+elseif(i2c->dev_comp->timing_adjust)+max_clk_div=MAX_CLOCK_DIV_8BITS;elsemax_clk_div=1;for(clk_div=1;clk_div<=max_clk_div;clk_div++){clk_src=parent_clk/clk_div;+i2c->ac_timing.inter_clk_div=clk_div-1;if(target_speed>I2C_MAX_FAST_MODE_PLUS_FREQ){/* Set master code speed register */
@@ -907,8 +924,6 @@ static int mtk_i2c_set_speed_adjust_timing(struct mtk_i2c *i2c,break;}-i2c->ac_timing.inter_clk_div=clk_div-1;-return0;}
--
2.25.1
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From: Wolfram Sang <hidden> Date: 2021-10-02 06:28:24
On Fri, Sep 17, 2021 at 06:14:10PM +0800, Kewei Xu wrote:
The reason for the modification here is that the previous
offset information is incorrect, OFFSET_DEBUGSTAT = 0xE4 is
the correct value.
Fixes: 25708278f810 ("i2c: mediatek: Add i2c support for MediaTek MT8183")
Signed-off-by: Kewei Xu <redacted>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
I think this is too verbose and should be a debugging only patch not
really suited for upstream. But if you like it this way, then keep
the verbosity. However, dev_err is too strong, this really needs to be
dev_dbg. Timeouts can happen on an I2C bus, think about an EEPROM in a
long erase cycle while you want to read it. Perfectly normal.
quoted hunk
if (ret == 0) {- dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);+ dev_err(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);+ i2c_dump_register(i2c);
From: Wolfram Sang <hidden> Date: 2021-10-02 06:40:09
On Fri, Sep 17, 2021 at 06:14:14PM +0800, Kewei Xu wrote:
In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust
support"), we miss setting OFFSET_EXT_CONF register if
i2c->dev_comp->timing_adjust is false, now add it back.
Fixes: be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support")
Signed-off-by: Kewei Xu <redacted>
Reviewed-by: Qii Wang <qii.wang@mediatek.com>
From: Wolfram Sang <hidden> Date: 2021-10-02 06:40:56
On Fri, Sep 17, 2021 at 06:14:15PM +0800, Kewei Xu wrote:
In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust
support"), the I2C timing calculation has been revised to support
ac-timing adjustment, however that will break on some I2C components.
As a result we want to introduce a new setting "default-adjust-timing"
so those components can choose to use the old (default) timing algorithm.
Why can't the new calculation be updated in a way that it works for all
I2C components?
I think this is too verbose and should be a debugging only patch not
really suited for upstream. But if you like it this way, then keep
the verbosity. However, dev_err is too strong, this really needs to
be
dev_dbg. Timeouts can happen on an I2C bus, think about an EEPROM in
a
long erase cycle while you want to read it. Perfectly normal.
quoted
if (ret == 0) {
- dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs-
quoted
addr);
+ dev_err(i2c->dev, "addr: %x, transfer timeout\n", msgs-
quoted
addr);
+ i2c_dump_register(i2c);
Needs to stay dev_dbg as well.
Yes, It is used for debugging,but dump the value of value of the
register is very important for debugging,so we think it is
necessary. We will use dev_dbg to replace dev_err in V8. Thanks~
On Sat, 2021-10-02 at 08:40 +0200, Wolfram Sang wrote:
On Fri, Sep 17, 2021 at 06:14:15PM +0800, Kewei Xu wrote:
quoted
In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing
adjust
support"), the I2C timing calculation has been revised to support
ac-timing adjustment, however that will break on some I2C
components.
As a result we want to introduce a new setting "default-adjust-
timing"
so those components can choose to use the old (default) timing
algorithm.
Why can't the new calculation be updated in a way that it works for
all
I2C components?
Hi, In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing
adjust support"), the I2C timing calculation has been revised to
support ac-timing adjustment.But in our design, it will make
tSU,STA/tHD,STA/tSU,STO shorter when the slave device have clock-
stretching feature. Then we upload the commit a80f24945fcf ("i2c:
mediatek: Use scl_int_delay_ns to compensate clock-stretching") to
support adjusting tSU,STA/tHD,STA/tSU,STO when the slave device clock-
stretching. But if the slave device stretch the SCL line for too long
time, our design still cannot make tSU,STA/tHD,STA/tSU,STO meet spec.
However in the old (default) timing algorithm before the commit
be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support"),
tSU,STA/tHD,STA/tSU,STO can meet spec. So we want to define a new
setting "default-adjust-timing" for using the old (default) timing
algorithm. Thanks~
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From: Wolfram Sang <hidden> Date: 2021-10-11 10:56:58
Hi,
stretching. But if the slave device stretch the SCL line for too long
time, our design still cannot make tSU,STA/tHD,STA/tSU,STO meet spec.
Isn't the new algorithm broken if it cannot support clock stretching?
What was the problem of the old algorithm not meeting the spec?
However in the old (default) timing algorithm before the commit
be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support"),
tSU,STA/tHD,STA/tSU,STO can meet spec. So we want to define a new
setting "default-adjust-timing" for using the old (default) timing
algorithm."
What I still do not get: the old algorithm was able to handle clock
stretching. Why can't you update the new one to handle clock stretching
as well. I might be missing something, but what is it?
Happy hacking,
Wolfram
From: Wolfram Sang <hidden> Date: 2021-11-29 12:51:10
quoted
stretching. But if the slave device stretch the SCL line for too long
time, our design still cannot make tSU,STA/tHD,STA/tSU,STO meet spec.
Isn't the new algorithm broken if it cannot support clock stretching?
What was the problem of the old algorithm not meeting the spec?
quoted
However in the old (default) timing algorithm before the commit
be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support"),
tSU,STA/tHD,STA/tSU,STO can meet spec. So we want to define a new
setting "default-adjust-timing" for using the old (default) timing
algorithm."
What I still do not get: the old algorithm was able to handle clock
stretching. Why can't you update the new one to handle clock stretching
as well. I might be missing something, but what is it?
I am still interested. Especially in the last question. Is the last
question clear to you? I can explain some more otherwise.
On Mon, 2021-11-29 at 13:49 +0100, Wolfram Sang wrote:
quoted
quoted
stretching. But if the slave device stretch the SCL line for too
long
time, our design still cannot make tSU,STA/tHD,STA/tSU,STO meet
spec.
Isn't the new algorithm broken if it cannot support clock
stretching?
What was the problem of the old algorithm not meeting the spec?
quoted
However in the old (default) timing algorithm before the commit
be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support"),
tSU,STA/tHD,STA/tSU,STO can meet spec. So we want to define a new
setting "default-adjust-timing" for using the old (default)
timing
algorithm."
What I still do not get: the old algorithm was able to handle clock
stretching. Why can't you update the new one to handle clock
stretching
as well. I might be missing something, but what is it?
I am still interested. Especially in the last question. Is the last
question clear to you? I can explain some more otherwise.
Hi,Wolfram,
I'm very sorry that I didn't reply to your information in time due
to my many personal affairs.
The Old algorithm was designed to focus only on normal functions, and
need to add additional custom code to adjust ac-timing when the
communication timing did not meet the specifications. so when there is
no clock stretch, ac-timing does not meet the spec, but the function is
always normal.
The new algorithm(The commit patch: be5ce0e97cc7 ("i2c: mediatek: Add
i2c ac-timing adjust support") is based on the requirements of i2c spec
to calculate the hardware-related settings so that the function and ac-
timing are normal When there is no clock stretch or the clock stretch
time is short. When the stretching time is very long (>60us), i2c ac-
timing does not meet the specifications and causes function abnormal.
In order to make the i2c function normal, this patch was submitted,
that is, when the stretch is long, the old algorithm is used to ensure
the function is normal, and when the stretch is short, the new
algorithm is used to ensure that the ac-timing and function are normal.
We found that when the ac-timing calculation formula is updated, the
new algorithm can make i2c ac-timing meet the spec and function
normally. So we plan to replace this patch with a patch that updates
the calculation formula.
Thanks~
Kewei
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From: Wolfram Sang <hidden> Date: 2021-12-18 10:17:06
Hi Kewei!
I'm very sorry that I didn't reply to your information in time due
to my many personal affairs.
No worries, there is no pressure from my side. I hope you are all well
now!
We found that when the ac-timing calculation formula is updated, the
new algorithm can make i2c ac-timing meet the spec and function
normally. So we plan to replace this patch with a patch that updates
the calculation formula.
Cool! I'm glad this is possible.
Looking forward to the new patch,
Wolfram