Re: [EXT] Re: [PATCH v14 2/2] arm64: dts: imx8: Add jpeg encoder/decoder nodes

Hi Hans,

On Tue, 2021-09-14 at 09:11 +0200, Hans Verkuil wrote:

Caution: EXT Email

Hi Mirela,

On 19/06/2021 16:36, Mirela Rabulea (OSS) wrote:

quoted

From: Mirela Rabulea <mirela.rabulea@nxp.com>

Add dts for imaging subsytem, include jpeg nodes here.
Tested on imx8qxp/qm.

I've posted a pull request for the first bindings patch for v5.16, so
this dts patch can be merged
through whatever tree takes such dts patches.

Thanks for the notice. I see the patch is already in linux-next. Any
 more action required from my behalf?

Regards,
Mirela

Regards,

        Hans

quoted

Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
---
Changes in v14:
  Address feedback from Aisheng Dong and Ezequiel Garcia:
    - use imx8 instead of imx in patch subject
    - keep jpeg and LPCGs used by jpeg enabled by default in
platform dts (no change here)

 .../arm64/boot/dts/freescale/imx8-ss-img.dtsi | 80
+++++++++++++++++++
 .../boot/dts/freescale/imx8qm-ss-img.dtsi     | 12 +++
 arch/arm64/boot/dts/freescale/imx8qm.dtsi     |  2 +
 .../boot/dts/freescale/imx8qxp-ss-img.dtsi    | 13 +++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  2 +
 5 files changed, 109 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-
img.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-
img.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi

b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
new file mode 100644
index 000000000000..a90654155a88

--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi

@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ * Zhou Guoniu <guoniu.zhou@nxp.com>
+ */
+img_subsys: bus@58000000 {
+     compatible = "simple-bus";
+     #address-cells = <1>;
+     #size-cells = <1>;
+     ranges = <0x58000000 0x0 0x58000000 0x1000000>;
+
+     img_ipg_clk: clock-img-ipg {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <200000000>;
+             clock-output-names = "img_ipg_clk";
+     };
+
+     jpegdec: jpegdec@58400000 {
+             reg = <0x58400000 0x00050000>;
+             interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+             clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
+                      <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
+             clock-names = "per", "ipg";
+             assigned-clocks = <&img_jpeg_dec_lpcg

IMX_LPCG_CLK_0>,
+                               <&img_jpeg_dec_lpcg
IMX_LPCG_CLK_4>;
+             assigned-clock-rates = <200000000>, <200000000>;
+             power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
+                             <&pd IMX_SC_R_MJPEG_DEC_S0>,
+                             <&pd IMX_SC_R_MJPEG_DEC_S1>,
+                             <&pd IMX_SC_R_MJPEG_DEC_S2>,
+                             <&pd IMX_SC_R_MJPEG_DEC_S3>;
+     };
+
+     jpegenc: jpegenc@58450000 {
+             reg = <0x58450000 0x00050000>;
+             interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+                          <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+             clocks = <&img_jpeg_enc_lpcg IMX_LPC[GIT PULL FOR
v5.16]G_CLK_0>,
+                      <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
+             clock-names = "per", "ipg";
+             assigned-clocks = <&img_jpeg_enc_lpcg
IMX_LPCG_CLK_0>,
+                               <&img_jpeg_enc_lpcg
IMX_LPCG_CLK_4>;
+             assigned-clock-rates = <200000000>, <200000000>;
+             power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
+                             <&pd IMX_SC_R_MJPEG_ENC_S0>,
+                             <&pd IMX_SC_R_MJPEG_ENC_S1>,
+                             <&pd IMX_SC_R_MJPEG_ENC_S2>,
+                             <&pd IMX_SC_R_MJPEG_ENC_S3>;
+     };
+
+     img_jpeg_dec_lpcg: clock-controller@585d0000 {
+             compatible = "fsl,imx8qxp-lpcg";
+             reg = <0x585d0000 0x10000>;
+             #clock-cells = <1>;
+             clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+             clock-indices = <IMX_LPCG_CLK_0>,
+                             <IMX_LPCG_CLK_4>;
+             clock-output-names = "img_jpeg_dec_lpcg_clk",
+                                  "img_jpeg_dec_lpcg_ipg_clk";
+             power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
+     };
+
+     img_jpeg_enc_lpcg: clock-controller@585f0000 {
+             compatible = "fsl,imx8qxp-lpcg";
+             reg = <0x585f0000 0x10000>;
+             #clock-cells = <1>;
+             clocks = <&img_ipg_clk>, <&img_ipg_clk>;
+             clock-indices = <IMX_LPCG_CLK_0>,
+                             <IMX_LPCG_CLK_4>;
+             clock-output-names = "img_jpeg_enc_lpcg_clk",
+                                  "img_jpeg_enc_lpcg_ipg_clk";
+             power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
+     };
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi

b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi
new file mode 100644
index 000000000000..7764b4146e0a

--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&jpegdec {
+     compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
+};
+
+&jpegenc {
+     compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi

b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 12cd059b339b..aebbe2b84aa1 100644

--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi

@@ -166,11 +166,13 @@
      };

      /* sorted in register address */
+     #include "imx8-ss-img.dtsi"
      #include "imx8-ss-dma.dtsi"
      #include "imx8-ss-conn.dtsi"
      #include "imx8-ss-lsio.dtsi"
 };

+#include "imx8qm-ss-img.dtsi"
 #include "imx8qm-ss-dma.dtsi"
 #include "imx8qm-ss-conn.dtsi"
 #include "imx8qm-ss-lsio.dtsi"

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi

b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
new file mode 100644
index 000000000000..3a087317591d

--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&jpegdec {
+     compatible = "nxp,imx8qxp-jpgdec";
+};
+
+&jpegenc {
+     compatible = "nxp,imx8qxp-jpgenc";
+};

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi

b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 1e6b4995091e..a625fb6bdc62 100644

--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi

@@ -258,12 +258,14 @@
      };

      /* sorted in register address */
+     #include "imx8-ss-img.dtsi"
      #include "imx8-ss-adma.dtsi"
      #include "imx8-ss-conn.dtsi"
      #include "imx8-ss-ddr.dtsi"
      #include "imx8-ss-lsio.dtsi"
 };

+#include "imx8qxp-ss-img.dtsi"
 #include "imx8qxp-ss-adma.dtsi"
 #include "imx8qxp-ss-conn.dtsi"
 #include "imx8qxp-ss-lsio.dtsi"

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