[PATCH 01/22] clk: sunxi-ng: v3s: Make the ISP PLL clock public
From: Paul Kocialkowski <hidden>
Date: 2021-09-10 18:42:23
Also in:
linux-clk, linux-devicetree, linux-media, linux-phy, linux-staging, linux-sunxi, lkml
Subsystem:
arm/allwinner sunxi soc support, common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
In order to reparent the CSI module clock to the ISP PLL via device-tree, export the ISP PLL clock declaration in the public device-tree header. Details regarding why the CSI module clock is best parented to the ISP PLL are provided in the related commit. Signed-off-by: Paul Kocialkowski <redacted> --- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 1 - include/dt-bindings/clock/sun8i-v3s-ccu.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
index 108eeeedcbf7..48e7e2b9fcf8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h@@ -23,7 +23,6 @@ #define CLK_PLL_DDR0 8 #define CLK_PLL_PERIPH0 9 #define CLK_PLL_PERIPH0_2X 10 -#define CLK_PLL_ISP 11 #define CLK_PLL_PERIPH1 12 /* Reserve one number for not implemented and not used PLL_DDR1 */
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
index 014ac6123d17..75f15e2d5404 100644
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h@@ -46,6 +46,7 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ #define _DT_BINDINGS_CLK_SUN8I_V3S_H_ +#define CLK_PLL_ISP 11 #define CLK_CPU 14 #define CLK_BUS_CE 20
--
2.32.0
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