Re: [PATCH v3] mtd: spinand: add support for Foresee FS35ND0*G parts
From: Daniel Palmer <hidden>
Date: 2021-08-23 16:14:28
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Hi Miquel, Thank you for your patience on this.. On Tue, 24 Aug 2021 at 00:03, Miquel Raynal [off-list ref] wrote:
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ECC: 3 corrected bitflip(s) at offset 0x08000000 0x08000000: fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|How is this result possible? You are dumping with the ECC engine enabled, it reports 3 bf (meaning that it is actually running, at least the software really thinks there is an on-die engine enabled) but the data has not been corrected. I expect the first byte to be 0xFF after correction. Only with -n (raw dump) we should see this.
I did a bit of searching to see if a newer/more detailed datasheet has come about and found some vendor code I hadn't seen before: https://github.com/100askTeam/NezaD1_u-boot-2018/blob/1f8b282626f0b9f29f96c57d6b1a5d728e523893/drivers/mtd/awnand/spinand/physic/core.c#L46 This says the ECC enable bit is non-standard and in a register that isn't documented at all in the datasheet. I guess the spi nand core isn't able to actually control the ECC on these chips at the moment and flipping the bits is updating the ECC too. Or the ECC isn't enabled at all. I couldn't see an easy way of overriding which register gets updated so I haven't tried it yet. Cheers, Daniel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel