Re: [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC
flat view
From: Samuel Holland <samuel@sholland.org>
Date: 2021-08-20 02:59:16
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On 8/2/21 1:22 AM, Icenowy Zheng wrote:
Allwinner R329 is a new SoC focused on smart audio devices. Add a DTSI file for it. Signed-off-by: Icenowy Zheng <redacted> --- .../arm64/boot/dts/allwinner/sun50i-r329.dtsi | 244 ++++++++++++++++++ 1 file changed, 244 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi
One comment below.
All of my other concerns are about the CCU and RTC bindings, which I have
commented on elsewhere.
Regards,
Samuel
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi new file mode 100644 index 000000000000..bfefa2b734b0 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi@@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Sipeed + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun50i-r329-ccu.h> +#include <dt-bindings/reset/sun50i-r329-ccu.h> +#include <dt-bindings/clock/sun50i-r329-r-ccu.h> +#include <dt-bindings/reset/sun50i-r329-r-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pio: pinctrl@2000400 { + compatible = "allwinner,sun50i-r329-pinctrl"; + reg = <0x02000400 0x400>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
There is an IRQ documented for port C (at SPI 70). Do those pins possibly have
interrupt capability?
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+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>;
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