[PATCH v2 1/9] dt-bindings: phy: mediatek: tphy: support type switch by pericfg
From: Chunfeng Yun <chunfeng.yun@mediatek.com>
Date: 2021-08-11 09:19:37
Also in:
dri-devel, linux-devicetree, linux-mediatek, linux-phy, lkml
Subsystem:
arm/mediatek usb3 phy driver, generic phy framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Chunfeng Yun, Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add support type switch by pericfg register between USB3, PCIe, SATA, SGMII, this is used to replace the way through efuse or jumper. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- v2: add reviewed-by Rob --- .../devicetree/bindings/phy/mediatek,tphy.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index 838852cb8527..9e6c0f43f1c6 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml@@ -201,6 +201,22 @@ patternProperties: Specify the flag to enable BC1.2 if support it type: boolean + mediatek,syscon-type: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + A phandle to syscon used to access the register of type switch, + the field should always be 3 cells long. + items: + items: + - description: + The first cell represents a phandle to syscon + - description: + The second cell represents the register offset + - description: + The third cell represents the index of config segment + enum: [0, 1, 2, 3] + required: - reg - "#phy-cells"
--
2.25.1
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