-----Original Message-----
From: Ulf Hansson <redacted>
Sent: Friday, August 6, 2021 6:36 PM
To: A, Rashmi <redacted>
Cc: <redacted>; Michal Simek
[off-list ref]; linux-mmc [off-list ref]; Linux
ARM [off-list ref]; Linux Kernel Mailing List <linux-
kernel@vger.kernel.org>; Kishon [off-list ref]; Vinod Koul
[off-list ref]; Andy Shevchenko
[off-list ref]; linux-phy@lists.infradead.org; Mark
Gross [off-list ref]; kris.pan@linux.intel.com; Zhou, Furong
[off-list ref]; Sangannavar, Mallikarjunappa
[off-list ref]; Hunter, Adrian
[off-list ref]; Vaidya, Mahesh R
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[off-list ref]
Subject: Re: [PATCH 2/3] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC
support to the arasan eMMC driver
On Fri, 30 Jul 2021 at 08:33, [off-list ref] wrote:
quoted
From: Rashmi A <redacted>
Intel Thunder Bay SoC eMMC controller is based on Arasan eMMC 5.1 host
controller IP
Signed-off-by: Rashmi A <redacted>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Rashmi, is it safe to apply this separately from the phy driver/dt changes?
Then I can queue this via my mmc tree, if you like.
No, the phy driver/dt changes must go together with "mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver" patch.
Regards
Rashmi
Kind regards
Uffe
quoted
---
drivers/mmc/host/sdhci-of-arasan.c | 29
++++++++++++++++++++++++++++-
quoted
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 839965f7c717..6f202fb7a546 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -185,6 +185,13 @@ static const struct sdhci_arasan_soc_ctl_map
intel_lgm_sdxc_soc_ctl_map = {quoted
.hiword_update = false,
};
+static const struct sdhci_arasan_soc_ctl_map thunderbay_soc_ctl_map = {
+ .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
+ .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
+ .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
+ .hiword_update = false,
+};
+
static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map
= {quoted
.baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
.clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, @@
-430,6 +437,15 @@ static const struct sdhci_pltfm_data
sdhci_arasan_cqe_pdata = {quoted
SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
};
+static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = {
+ .ops = &sdhci_arasan_cqe_ops,
+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
quoted
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
+ SDHCI_QUIRK2_STOP_WITH_TC |
+ SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
+};
+
#ifdef CONFIG_PM_SLEEP
/**
* sdhci_arasan_suspend - Suspend method for the driver @@ -1098,6
+1114,12 @@ static struct sdhci_arasan_of_data
sdhci_arasan_generic_data = {quoted
.clk_ops = &arasan_clk_ops,
};
+static const struct sdhci_arasan_of_data sdhci_arasan_thunderbay_data =
{quoted
+ .soc_ctl_map = &thunderbay_soc_ctl_map,
+ .pdata = &sdhci_arasan_thunderbay_pdata,
+ .clk_ops = &arasan_clk_ops,
+};
+
static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
.ops = &sdhci_arasan_cqe_ops,
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | @@ -1231,6
+1253,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
.compatible = "intel,keembay-sdhci-5.1-sdio",
.data = &intel_keembay_sdio_data,
},
+ {
+ .compatible = "intel,thunderbay-sdhci-5.1",
+ .data = &sdhci_arasan_thunderbay_data,
+ },
/* Generic compatible below here */
{
.compatible = "arasan,sdhci-8.9a", @@ -1582,7 +1608,8@@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
- of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
+ of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio") ||
+ of_device_is_compatible(np, "intel,thunderbay-sdhci-5.1"))
+ {
sdhci_arasan_update_clockmultiplier(host, 0x0);
sdhci_arasan_update_support64b(host, 0x0);
--2.17.1
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