[PATCH v2 01/14] dt-bindings: mediatek: add vdosys1 RDMA/MERGE definition for mt8195
From: Nancy.Lin <hidden>
Date: 2021-07-22 09:58:29
Also in:
dri-devel, linux-mediatek
Subsystem:
drm drivers, drm drivers and misc gpu patches, drm drivers for mediatek, open firmware and flattened device tree bindings, the rest · Maintainers:
David Airlie, Simona Vetter, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Chun-Kuang Hu, Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add vdosys1 RDMA and MERGE definition. Signed-off-by: Nancy.Lin <redacted> --- .../display/mediatek/mediatek,disp.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..b5a80c683ef6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml@@ -230,6 +230,14 @@ properties: - items: - const: mediatek,mt8173-disp-od + # RDMA: read DMA + - items: + - const: mediatek,mt8195-vdo1-rdma + + # MERGE: merge streams from two RDMA sources + - items: + - const: mediatek,mt8195-vdo1-merge + reg: description: Physical base address and length of the function block register space.
@@ -461,4 +469,26 @@ examples: /* See mediatek,dsc.yaml for details */ }; + vdo1_rdma0: vdo1_rdma@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + merge1: disp_vpp_merge@1c10c000 { + compatible = "mediatek,mt8195-vdo1-merge"; + reg = <0 0x1c10c000 0 0x1000>; + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; + }; + ...
--
2.18.0
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