[PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set

Subsystems: arm64 port (aarch64 architecture), kernel virtual machine for arm64 (kvm/arm64), the rest

STALE1872d LANDED

Landed in mainline as 2a71fabf6a1b on 2021-06-18.

3 messages, 2 authors, 2021-06-18 · open the first message on its own page

[PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set

From: Alexandru Elisei <hidden>
Date: 2021-06-18 10:52:25 

According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:

"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."

Similar behaviour is described for AArch32 on page G8-7022. Make it so.

Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <redacted>
---
Found by code inspection.

Entertained the idea of restricting the number of bits in
for_each_set_bit() to 31 since Linux (and the architecture, to some degree)
treats the cycle count register as the 32nd event counter. Settled on this
approach because I think it's clearer.

 arch/arm64/kvm/pmu-emul.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index fd167d4f4215..ecc0d19c8cc1 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
 		kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
 
 	if (val & ARMV8_PMU_PMCR_P) {
+		mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
 		for_each_set_bit(i, &mask, 32)
 			kvm_pmu_set_counter_value(vcpu, i, 0);
 	}
-- 
2.32.0


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Re: [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set

From: Alexandru Elisei <hidden>
Date: 2021-06-18 11:17:42 

Argh, forgot to CC Eric.

On 6/18/21 11:51 AM, Alexandru Elisei wrote:
quoted hunk
According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:

"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."

Similar behaviour is described for AArch32 on page G8-7022. Make it so.

Fixes: c01d6a18023b ("KVM: arm64: pmu: Only handle supported event counters")
Signed-off-by: Alexandru Elisei <redacted>
---
Found by code inspection.

Entertained the idea of restricting the number of bits in
for_each_set_bit() to 31 since Linux (and the architecture, to some degree)
treats the cycle count register as the 32nd event counter. Settled on this
approach because I think it's clearer.

 arch/arm64/kvm/pmu-emul.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index fd167d4f4215..ecc0d19c8cc1 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -578,6 +578,7 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
 		kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0);
 
 	if (val & ARMV8_PMU_PMCR_P) {
+		mask &= ~BIT(ARMV8_PMU_CYCLE_IDX);
 		for_each_set_bit(i, &mask, 32)
 			kvm_pmu_set_counter_value(vcpu, i, 0);
 	}
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Re: [PATCH] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set

From: Marc Zyngier <maz@kernel.org>
Date: 2021-06-18 13:24:51 

On Fri, 18 Jun 2021 11:51:39 +0100, Alexandru Elisei wrote:
According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to
1 has the following effect:

"Reset all event counters accessible in the current Exception level, not
including PMCCNTR_EL0, to zero."

Similar behaviour is described for AArch32 on page G8-7022. Make it so.
Applied to kvm-arm64/pmu-fixes, thanks!

[1/1] KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set
      commit: 2a71fabf6a1bc9162a84e18d6ab991230ca4d588

Cheers,

	M.
-- 
Without deviation from the norm, progress is not possible.



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