Re: [PATCH v1 3/5] arm64: dts: mt8195: add gce node
From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date: 2021-06-30 23:23:07
Also in:
linux-devicetree, linux-mediatek, lkml
Hi, Jason: jason-jh.lin [off-list ref] 於 2021年6月30日 週三 下午1:18寫道：
quoted hunk ↗ jump to hunk
add gce node on dts file. Change-Id: I805455cb7c645cb5a24ce1c87fe891a807069123 Signed-off-by: jason-jh.lin <redacted> --- This patch is based on [1] [1] Add Mediatek SoC MT8195 and evaluation board dts and Makefile - https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/ --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c146a91c6272..38054196eea4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi@@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/clock/mt8195-clk.h> +#include <dt-bindings/gce/mt8195-gce.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/mt8195-power.h>@@ -717,6 +718,26 @@ #clock-cells = <1>; }; + gce0: mdp_mailbox@10320000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <3>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>, + <&infracfg_ao CLK_INFRA_AO_GCE2>; + clock-names = "gce", "gce1"; + }; + + gce1: disp_mailbox@10330000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <3>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>, + <&infracfg_ao CLK_INFRA_AO_GCE2>; + clock-names = "gce", "gce1";
I think each gce could be broken into two function block, the core function block and event processing block. Each block has independent clock source and "gce" is for core function block and "gce1" is for event processing block, is it? If so, the core function of gce0 and gce1 has common clock source (<&infracfg_ao CLK_INFRA_AO_GCE>), right? Regards, Chun-Kuang.
+ };
+
uart0: serial@11001100 {
compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
reg = <0 0x11001100 0 0x100>;
--
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