RE: [PATCH] arm64: dts: imx8mm: add pgc/blk_ctl nodes
From: Peng Fan <peng.fan@nxp.com>
Date: 2021-06-30 09:36:58
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Subject: Re: [PATCH] arm64: dts: imx8mm: add pgc/blk_ctl nodes On Fri, Jun 4, 2021 at 5:37 AM Peng Fan (OSS) [off-list ref] wrote:quoted
From: Peng Fan <peng.fan@nxp.com> With PGC and BLK-CTL landed, we could add pgc and blk-ctl nodes, because some pgc domain relies on blk-ctl power domain, so they need to be added together. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V1: Depends on the blk-ctl patchset, https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F202105221342 49quoted
.15322-1-peng.fan%40oss.nxp.com%2F&data=04%7C01%7Cpeng.fan%40nxp.cquoted
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Shawn, Since the blk-ctl patchset is in good shape and tested, is it ok for you to pick up? Thanks arch/arm64/boot/dts/freescale/imx8mm.dtsi | 128 ++++++++++++++++++++++ 1 file changed, 128 insertions(+)diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsib/arch/arm64/boot/dts/freescale/imx8mm.dtsi index e7648c3b8390..0e01ff649956 100644--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi@@ -7,6 +7,8 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/imx8mm-power.h> +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/thermal/thermal.h> #include "imx8mm-pinfunc.h"@@ -609,6 +611,109 @@ src: reset-controller@30390000 { interrupts = <GIC_SPI 89IRQ_TYPE_LEVEL_HIGH>;quoted
#reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupts = <GIC_SPI 87IRQ_TYPE_LEVEL_HIGH>;quoted
+ interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix:power-domain@0 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_HSIOMIX>;quoted
+ clocks = <&clkIMX8MM_CLK_USB1_CTRL_ROOT>;quoted
+ }; + + pgc_pcie:power-domain@1 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_PCIE>;quoted
+ power-domains= <&pgc_hsiomix>;quoted
+ clocks = <&clkIMX8MM_CLK_PCIE1_ROOT>;quoted
+ }; + + pgc_otg1:power-domain@2 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_OTG1>;quoted
+ power-domains= <&pgc_hsiomix>;quoted
+ }; + + pgc_otg2:power-domain@3 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_OTG2>;quoted
+ power-domains= <&pgc_hsiomix>;quoted
+ }; +Any change you could add the references to pgc_otg1 and pgc_otg2 to their respective OTG nodes? Without them, enabling OTG1 or OTG2 can result in a hang unless it was started in U-Boot.
Will post v2 to add that, really hope the driver part could be in, then move on. Thanks, Peng.
quoted
+ pgc_gpumix:power-domain@4 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_GPUMIX>;quoted
+ clocks = <&clkIMX8MM_CLK_GPU_BUS_ROOT>,quoted
+<&clk IMX8MM_CLK_GPU_AHB>;quoted
+ }; + + pgc_gpu:power-domain@5 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_GPU>;quoted
+ clocks = <&clkIMX8MM_CLK_GPU_AHB>,quoted
+<&clk IMX8MM_CLK_GPU_BUS_ROOT>,quoted
+<&clk IMX8MM_CLK_GPU2D_ROOT>,quoted
+<&clk IMX8MM_CLK_GPU3D_ROOT>;quoted
+ resets = <&srcIMX8MQ_RESET_GPU_RESET>;quoted
+ power-domains= <&pgc_gpumix>;quoted
+ }; + + pgc_vpumix:power-domain@6 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_VPUMIX>;quoted
+ clocks = <&clkIMX8MM_CLK_VPU_DEC_ROOT>;quoted
+ resets = <&srcIMX8MQ_RESET_VPU_RESET>;quoted
+ }; + + pgc_vpu_g1:power-domain@7 {quoted
+#power-domain-cells = <0>;quoted
+ power-domains=quoted
+<&vpumix_blk_ctl IMX8MM_BLK_CTL_PD_VPU_BUS>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_VPUG1>;quoted
+ clocks = <&clkIMX8MM_CLK_VPU_G1_ROOT>;quoted
+ }; + + pgc_vpu_g2:power-domain@8 {quoted
+#power-domain-cells = <0>;quoted
+ power-domains=quoted
+<&vpumix_blk_ctl IMX8MM_BLK_CTL_PD_VPU_BUS>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_VPUG2>;quoted
+ clocks = <&clkIMX8MM_CLK_VPU_G2_ROOT>;quoted
+ }; + + pgc_vpu_h1:power-domain@9 {quoted
+#power-domain-cells = <0>;quoted
+ power-domains=quoted
+<&vpumix_blk_ctl IMX8MM_BLK_CTL_PD_VPU_BUS>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_VPUH1>;quoted
+ clocks = <&clkIMX8MM_CLK_VPU_H1_ROOT>;quoted
+ }; + + pgc_dispmix:power-domain@10 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_DISPMIX>;quoted
+ clocks = <&clkIMX8MM_CLK_DISP_ROOT>,quoted
+<&clk IMX8MM_CLK_DISP_AXI_ROOT>,quoted
+<&clk IMX8MM_CLK_DISP_APB_ROOT>;quoted
+ }; + + pgc_mipi:power-domain@11 {quoted
+#power-domain-cells = <0>;quoted
+ reg =<IMX8MM_POWER_DOMAIN_MIPI>;quoted
+ power-domains=quoted
+<&dispmix_blk_ctl IMX8MM_BLK_CTL_PD_DISPMIX_BUS>;quoted
+ }; + }; + }; }; aips2: bus@30400000 {@@ -960,6 +1065,18 @@ aips4: bus@32c00000 { #size-cells = <1>; ranges = <0x32c00000 0x32c000000x400000>;quoted
+ dispmix_blk_ctl: blk_ctl@32e28000 { + compatible ="fsl,imx8mm-dispmix-blk-ctl", "syscon";quoted
+ reg = <0x32e28000 0x100>; + #power-domain-cells = <1>; + #reset-cells = <1>; + power-domains = <&pgc_dispmix>,<&pgc_mipi>;quoted
+ power-domain-names = "dispmix","mipi";quoted
+ clocks = <&clkIMX8MM_CLK_DISP_ROOT>,quoted
+ <&clkIMX8MM_CLK_DISP_AXI_ROOT>,quoted
+ <&clkIMX8MM_CLK_DISP_APB_ROOT>;quoted
+ }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb","fsl,imx7d-usb";quoted
reg = <0x32e40000 0x200>; @@-1029,6quoted
+1146,17 @@ gpmi: nand-controller@33002000{ status = "disabled"; }; + vpumix_blk_ctl: blk-ctl@38330000 { + compatible = "fsl,imx8mm-vpumix-blk-ctl","syscon";quoted
+ reg = <0x38330000 0x100>; + #power-domain-cells = <1>; + #reset-cells = <1>; + power-domains = <&pgc_vpumix>,<&pgc_vpu_g1>, <&pgc_vpu_g2>, <&pgc_vpu_h1>;quoted
+ power-domain-names = "vpumix", "vpu-g1","vpu-g2", "vpu-h1";quoted
+ clocks = <&clkIMX8MM_CLK_VPU_DEC_ROOT>, <&clk IMX8MM_CLK_VPU_G1_ROOT>,quoted
+ <&clkIMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_H1_ROOT>;quoted
+ }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ -- 2.30.0
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