Hello Sean,

On Fri, Jun 25, 2021 at 01:46:26PM -0400, Sean Anderson wrote:

On 6/25/21 12:56 PM, Uwe Kleine-König wrote:

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On Fri, Jun 25, 2021 at 11:13:33AM -0400, Sean Anderson wrote:

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On 6/25/21 2:19 AM, Uwe Kleine-König wrote:

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On Fri, May 28, 2021 at 05:45:22PM -0400, Sean Anderson wrote:

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+ * - Cannot produce 100% duty cycle.

Can it produce a 0% duty cycle? Below you're calling
xilinx_timer_tlr_period(..., ..., ..., 0) then which returns -ERANGE.

Yes. This is what you get when you try to specify 100% duty cycle (e.g.
TLR0 == TLR1).

OK, so the hardware can do it, but your driver doesn't make use of it,
right?

So to clarify, I have observed the following behavior

* When TCSR == 0, the output is constant low.
* When TLR1 (duty_cycle) >= TLR0 (period), the output is constant low.

It might be possible to achieve constant high output by stopping the
counters during the high time, but leaving the PWM bit set. However, I
do not have a use case for this. I think it might be a nice follow-up
for someone who wants that feature.

A typical use case is having an LED or a backlight connected to the PWM
and and want it to be fully on.

That being said, is there a standard way to specify 100% or 0% duty
cycle? It seems like one would have to detect these situations and use a
different code path.

I don't understand that question. If pwm_apply_state is called with a
state having .duty_cycle = 0 (and .enabled = true) you're supposed to
emit a 0% relative duty. If .duty_cycle = .period is passed you're
supposed to emit a 100% relative duty.

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+ * - Only produces "normal" output.

Does the output emit a low level when it's disabled?

I believe so.

Is there a possibility to be sure? I'd like to know that to complete my
picture about the behaviour of the supported PWMs.

See above.

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+static int xilinx_pwm_apply(struct pwm_chip *chip, struct pwm_device *unused,
+			    const struct pwm_state *state)
+{
+	int ret;
+	struct xilinx_timer_priv *priv = xilinx_pwm_chip_to_priv(chip);
+	u32 tlr0, tlr1;
+	u32 tcsr0 = xilinx_timer_read(priv, TCSR0);
+	u32 tcsr1 = xilinx_timer_read(priv, TCSR1);
+	bool enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1);
+
+	if (state->polarity != PWM_POLARITY_NORMAL)
+		return -EINVAL;
+
+	ret = xilinx_timer_tlr_period(priv, &tlr0, tcsr0, state->period);
+	if (ret)
+		return ret;

The implementation of xilinx_timer_tlr_period (in patch 2/3) returns
-ERANGE for big periods. The good behaviour to implement is to cap to
the biggest period possible in this case.

Ok. Is this documented anywhere?

I tried but Thierry didn't like the result and I didn't retry. The
problem is also that many drivers we already have in the tree don't
behave like this (because for a long time nobody cared). That new
drivers should behave this way is my effort to get some consistent
behaviour.

Do you have a link to the thread? IMO if you would like to specify
behavior like this, is is very helpful to write it down so new authors
don't have to get to v4 before finding out about it ;)

I misremembered, the last time I wanted to improve the documentation I
didn't write anything about the policy with the goal to improve the
documentation without hitting the a bit controversial policy stuff. The
thread is available at

	https://lore.kernel.org/r/20191209213233.29574-2-u.kleine-koenig@pengutronix.de (local)

. Thierry didn't reply to this thread yet.

My intension was to build on this one and formulate the expected policy
for new drivers.

The situation I'm in here wanting to install this policy is: On one hand
Thierry argues that consumers don't care much about how .apply rounds
because most consumers just don't have so exact requirements. And on the
other hand he doesn't want to change the existing behaviour for already
existing drivers to not break consumers. So the best I can currently to
do work on a more consistent behaviour is to enforce this for new
drivers.

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And wouldn't this result in the wrong duty cycle? E.g. say the max
value is 100 and I try to apply a period of 150 and a duty_cycle of 75
(for a 50% duty cycle). If we cap at 100, then I will instead have a
75% duty cycle, and there will be no error.

Yes that is right. That there is no feedback is a problem that we have
for a long time. I have a prototype patch that implements a
pwm_round_state() function that lets a consumer know the result of
applying a certain pwm_state in advance. But we're not there yet.

So for the moment, why not give an error? This will be legal code both
now and after round_state is implemented.

The problem is where to draw the line. To stay with your example: If a
request for period = 150 ns comes in, and let X be the biggest period <=
150 ns that the hardware can configure. For which values of X should an
error be returned and for which values the setting should be
implemented.

In my eyes the only sensible thing to implement here is to tell the
consumer about X and let it decide if it's good enough. If you have a
better idea let me hear about it.

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So I will silently get the wrong duty cycle, even when that duty cycle
is probably more important than the period.

It depends on the use case and every policy is wrong for some cases. So
I picked the policy I already explained because it is a) easy to
implement for lowlevel drivers and b) it's easy to work with for
consumers once we have pwm_round_state().

What about sysfs? Right now if you try to specify an inexpressible
period you get an error message. I saw [1], but unfortunately there do
not appear to be any patches associated with it. Do you have plans to
implement such an interface?

[1] https://lore.kernel.org/linux-pwm/CAO1O6seyi+1amAY5YLz0K1dkNd7ewAvot4K1eZMpAAQquz0-9g@mail.gmail.com/ (local)

In my eyes we better implement a pwmctl interface that doesn't work via
sysfs but using an ioctl; similar what gpio did with gpioctl for various
reasons.

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Also note that state->period is an u64 but it is casted to unsigned int
as this is the type of the forth parameter of xilinx_timer_tlr_period.

Hm, it looks like I immediately cast period to a u64. I will change the
signature for this function next revision.

Then note that period * clk_get_rate(priv->clk) might overflow.

Ok, so is mult_frac the correct macro to use here?

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+	ret = xilinx_timer_tlr_period(priv, &tlr1, tcsr1, state->duty_cycle);
+	if (ret)
+		return ret;

Perhaps I should add

	if (tlr0 <= tlr1)
		return -EINVAL;

here to prevent accidentally getting 0% duty cycle.

You can assume that duty_cycle <= period when .apply is called.

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+	else if (pwm_cells)
+		return dev_err_probe(dev, -EINVAL, "#pwm-cells must be 0\n");

What is the rationale here to not support #pwm-cells = <2>?

Only one PWM is supported. But otherwise there is no particular
reason.

The usual binding is to have 3 additional parameters.
  1) chip-local pwm number (which can only be 0 for a pwmchip having
     .npwm = 1)
  2) the "typical" period
  3) some flags (like PWM_POLARITY_*)

I don't care much if you implement it with or without 1), but 2) and 3)
should IMHO be here. If you don't want 1),
http://patchwork.ozlabs.org/project/linux-pwm/patch/20210622030948.966748-1-bjorn.andersson@linaro.org/
might be interesting for you. (But note, Thierry didn't give feedback to
this yet, it might be possible he wants 1)-3) for new drivers.)

Ok, so since I let of_pwmchip_add set xlate, I don't need to change
anything in this driver? Then I will remove this check for v5.

Yes.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
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