Re: [PATCH v3 08/11] clk: renesas: Add CPG core wrapper for RZ/G2L SoC

Hi Geert,

Thank you for the review.

On Thu, Jun 10, 2021 at 2:04 PM Geert Uytterhoeven [off-list ref] wrote:

Hi Prabhakar,

On Wed, Jun 9, 2021 at 5:33 PM Lad Prabhakar
[off-list ref] wrote:

quoted

Add CPG core wrapper for RZ/G2L family.

Based on a patch in the BSP by Binh Nguyen
[off-list ref].

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

quoted

--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig

@@ -182,6 +182,11 @@ config CLK_RCAR_USB2_CLOCK_SEL
        help
          This is a driver for R-Car USB2 clock selector

+config CLK_RZG2L
+       bool "Renesas RZ/G2L SoC clock support" if COMPILE_TEST && !ARCH_RENESAS

s/SoC/family/?

Agreed.

I think "if COMPILE_TEST", as all other entries are using, is sufficient.

quoted

+       depends on ARCH_RENESAS || COMPILE_TEST

I think this can be dropped.

Agreed.

quoted

+       select RESET_CONTROLLER
+
 # Generic

quoted

--- /dev/null
+++ b/drivers/clk/renesas/renesas-rzg2l-cpg.c

quoted

+static struct clk
+*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
+                              void *data)
+{
+       unsigned int clkidx = clkspec->args[1];
+       struct rzg2l_cpg_priv *priv = data;
+       struct device *dev = priv->dev;
+       const char *type;
+       struct clk *clk;
+
+       switch (clkspec->args[0]) {
+       case CPG_CORE:
+               type = "core";
+               if (clkidx > priv->last_dt_core_clk) {
+                       dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
+                       return ERR_PTR(-EINVAL);
+               }
+               clk = priv->clks[clkidx];
+               break;
+
+       case CPG_MOD:
+               type = "module";
+               if (clkidx > priv->num_core_clks + priv->num_mod_clks) {

The range of module clocks in DT specifiers starts at zero, so

    if (clkidx > priv->num_mod_clks) {

Thanks for the catch, yes the above check should be good.

quoted

+                       dev_err(dev, "Invalid %s clock index %u\n", type,
+                               clkidx);
+                       return ERR_PTR(-EINVAL);
+               }
+               clk = priv->clks[priv->num_core_clks + clkidx];
+               break;
+
+       default:
+               dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
+               return ERR_PTR(-EINVAL);
+       }
+
+       if (IS_ERR(clk))
+               dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
+                       PTR_ERR(clk));
+       else
+               dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
+                       clkspec->args[0], clkspec->args[1], clk,
+                       clk_get_rate(clk));
+       return clk;
+}

With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

I can fix these while applying.

Thank you.

Cheers,
Prabhakar

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