Re: [PATCH v2 06/12] clk: renesas: Define RZ/G2L CPG Clock Definitions
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2021-06-08 15:25:45
Also in:
linux-clk, linux-devicetree, linux-renesas-soc, linux-serial, lkml
On Fri, Jun 4, 2021 at 12:18 AM Lad Prabhakar [off-list ref] wrote:
Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock
and module clock outputs, as listed in Table 8.3 ("Clock List")
of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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