Re: [boot-wrapper PATCH v3 2/8] aarch64: Rename labels and prepare for lower EL booting
From: Andre Przywara <andre.przywara@arm.com>
Date: 2021-05-25 10:36:54
On Tue, 25 May 2021 14:25:03 +0800 Jaxson Han [off-list ref] wrote: Hi,
Prepare for booting from lower EL. Rename *_el3 relavant labels with *_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means "We neither do init sequence at this highest EL nor drop to lower EL when entering to kernel", we rename it with _keep_el to make it more clear for lower EL initialisation.
Confirmed that it's only renaming of labels and extending and adding comments:
Signed-off-by: Jaxson Han <redacted>
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre
quoted hunk ↗ jump to hunk
--- arch/aarch64/boot.S | 31 +++++++++++++++++++++---------- arch/aarch64/psci.S | 13 +++++++------ arch/aarch64/spin.S | 8 ++++---- 3 files changed, 32 insertions(+), 20 deletions(-)diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index a9264de..1a5da35 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S@@ -12,7 +12,7 @@ .section .init .globl _start - .globl jump_kernel + .globl jump_kernel _start: cpuid x0, x1@@ -22,20 +22,31 @@ _start: bl setup_stack /* - * EL3 initialisation + * Boot sequence + * If CurrentEL == EL3, then goto EL3 initialisation and drop to + * lower EL before entering the kernel. + * Else, no initialisation and keep the current EL before + * entering the kernel. */ mrs x0, CurrentEL cmp x0, #CURRENTEL_EL3 - b.eq 1f + beq el3_init + /* + * We stay in the current EL for entering the kernel + */ mov w0, #1 - ldr x1, =flag_no_el3 + ldr x1, =flag_keep_el str w0, [x1] bl setup_stack - b start_no_el3 + b start_keep_el -1: mov x0, #0x30 // RES1 + /* + * EL3 initialisation + */ +el3_init: + mov x0, #0x30 // RES1 orr x0, x0, #(1 << 0) // Non-secure EL1 orr x0, x0, #(1 << 8) // HVC enable@@ -114,7 +125,7 @@ _start: bl gic_secure_init - b start_el3 + b start_el_max err_invalid_id: b .@@ -141,7 +152,7 @@ jump_kernel: bl find_logical_id bl setup_stack // Reset stack pointer - ldr w0, flag_no_el3 + ldr w0, flag_keep_el cmp w0, #0 // Prepare Z flag mov x0, x20@@ -150,7 +161,7 @@ jump_kernel: mov x3, x23 b.eq 1f - br x19 // No EL3 + br x19 // Keep current EL 1: mov x4, #SPSR_KERNEL@@ -168,5 +179,5 @@ jump_kernel: .data .align 3 -flag_no_el3: +flag_keep_el: .long 0diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S index 01ebe7d..ae02fd6 100644 --- a/arch/aarch64/psci.S +++ b/arch/aarch64/psci.S@@ -45,8 +45,8 @@ vector: .text - .globl start_no_el3 - .globl start_el3 + .globl start_keep_el + .globl start_el_max err_exception: b err_exception@@ -101,7 +101,7 @@ smc_exit: eret -start_el3: +start_el_max: ldr x0, =vector bl setup_vector@@ -111,10 +111,11 @@ start_el3: b psci_first_spin /* - * This PSCI implementation requires EL3. Without EL3 we'll only boot the - * primary cpu, all others will be trapped in an infinite loop. + * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2). + * Without the highest EL, we'll only boot the primary cpu, all others + * will be trapped in an infinite loop. */ -start_no_el3: +start_keep_el: cpuid x0, x1 bl find_logical_id cbz x0, psci_first_spindiff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index 72603cf..533177c 100644 --- a/arch/aarch64/spin.S +++ b/arch/aarch64/spin.S@@ -11,11 +11,11 @@ .text - .globl start_no_el3 - .globl start_el3 + .globl start_keep_el + .globl start_el_max -start_el3: -start_no_el3: +start_el_max: +start_keep_el: cpuid x0, x1 bl find_logical_id
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