Thread (29 messages) 29 messages, 3 authors, 2021-05-20
STALE1855d

[PATCH v2 05/16] arm64: Remove uaccess toggle from __flush_cache_range macro

From: Fuad Tabba <hidden>
Date: 2021-05-17 07:59:15
Subsystem: arm64 port (aarch64 architecture), the rest · Maintainers: Catalin Marinas, Will Deacon, Linus Torvalds

The uaccess toggle isn't part of the cache maintenance operation.
Move it directly to where it's needed.

No functional change intended.

Signed-off-by: Fuad Tabba <redacted>
---
 arch/arm64/mm/cache.S | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 6babaaf34f17..d74b20cd6449 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -26,9 +26,6 @@
  *	- needs_uaccess - (macro parameter) might access user space memory
  */
 .macro	__flush_cache_range, needs_uaccess
-	.if 	\needs_uaccess
-	uaccess_ttbr0_enable x2, x3, x4
-	.endif
 alternative_if ARM64_HAS_CACHE_IDC
 	dsb	ishst
 	b	7f
@@ -55,9 +52,6 @@ alternative_else_nop_endif
 	invalidate_icache_by_line x0, x1, x2, x3, \needs_uaccess, 9f
 8:	mov	x0, #0
 1:
-	.if	\needs_uaccess
-	uaccess_ttbr0_disable x1, x2
-	.endif
 	ret
 
 	.if 	\needs_uaccess
@@ -92,7 +86,9 @@ SYM_FUNC_END(__flush_icache_range)
  *	- end     - virtual end address of region
  */
 SYM_FUNC_START(__flush_cache_user_range)
+	uaccess_ttbr0_enable x2, x3, x4
 	__flush_cache_range needs_uaccess=1
+	uaccess_ttbr0_disable x1, x2
 SYM_FUNC_END(__flush_cache_user_range)
 
 /*
-- 
2.31.1.751.gd2f1c929bd-goog


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