Re: [PATCH v2 3/3] arm64/sve: Skip flushing Z registers with 128 bit vectors

On Wed, May 12, 2021 at 02:49:09PM +0100, Dave Martin wrote:

On Tue, May 11, 2021 at 05:04:46PM +0100, Mark Brown wrote:

quoted

+/*
+ * Zero all SVE registers but the first 128-bits of each vector
+ *
+ * x0 = VQ - 1

This does require that ZCR_EL1.LEN has already been set to match x0, and
is not changed again before entering userspace.

It would be a good idea to at least describe this in a comment so that
this doesn't get forgotten later on, but there's a limit to how
foolproof this low-level backend code needs to be...

Similar concerns exist for huge chunks of the existing SVE code (eg, the
no further changes on vector length constraint is pretty much universal
and is I'd say largely more of a "make sure you handle the register
contents" thing on anything that changes the vector length).