[PATCH 2/3 v3] crypto: ixp4xx: Add DT bindings
From: Linus Walleij <hidden>
Date: 2021-05-22 17:01:32
Also in:
linux-crypto, linux-devicetree
Subsystem:
crypto api, open firmware and flattened device tree bindings, the rest · Maintainers:
Herbert Xu, "David S. Miller", Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
This adds device tree bindings for the ixp4xx crypto engine. Cc: Corentin Labbe <clabbe@baylibre.com> Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <redacted> --- ChangeLog v2->v3: - Use the reg property to set the NPE instance number for the crypto engine. - Add address-cells and size-cells to the NPE bindings consequently. - Use a patternProperty to match the cryto engine child "crypto@N". - Define as crypto@2 in the example. - Describe the usage of the queue instance cell for the queue manager phandles. ChangeLog v1->v2: - Drop the phandle to self, just add an NPE instance number instead. - Add the crypto node to the NPE binding. - Move the example over to the NPE binding where it appears in context. --- .../bindings/crypto/intel,ixp4xx-crypto.yaml | 46 +++++++++++++++++++ ...ntel,ixp4xx-network-processing-engine.yaml | 21 +++++++++ 2 files changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
new file mode 100644
index 000000000000..9df2062e4816
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml@@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx cryptographic engine + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE + (Network Processing Engine). Since it is not a device on its own + it is defined as a subnode of the NPE, if crypto support is + available on the platform. + +properties: + compatible: + const: intel,ixp4xx-crypto + + reg: + minimum: 0 + maximum: 3 + description: instance number to the NPE this crypto engine is using + + queue-rx: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: phandle to the RX queue on the NPE, the cell describing + the queue instance to be used. + + queue-txready: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: phandle to the TX READY queue on the NPE, the cell describing + the queue instance to be used. + +required: + - compatible + - reg + - queue-rx + - queue-txready + +additionalProperties: false
diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
index 1bd2870c3a9c..8b2eaf835b66 100644
--- a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml@@ -30,6 +30,18 @@ properties: - description: NPE1 register range - description: NPE2 register range + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^crypto@[0-7]+$": + $ref: /schemas/crypto/intel,ixp4xx-crypto.yaml# + type: object + description: Optional node for the embedded crypto engine + required: - compatible - reg
@@ -41,5 +53,14 @@ examples: npe@c8006000 { compatible = "intel,ixp4xx-network-processing-engine"; reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + crypto@2 { + compatible = "intel,ixp4xx-crypto"; + reg = <2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; }; ...
--
2.31.1
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