RE: [PATCH] arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges
From: Claudiu Manoil <claudiu.manoil@nxp.com>
Date: 2021-05-11 09:48:28
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-----Original Message----- From: Shawn Guo <shawnguo@kernel.org> Sent: Tuesday, May 11, 2021 6:07 AM
[...]
Subject: Re: [PATCH] arm64: dts: fsl-ls1028a: Correct ECAM PCIE window ranges + Claudiu On Wed, Apr 07, 2021 at 02:34:38PM +0200, Kornel Duleba wrote:quoted
Currently all PCIE windows point to bus address 0x0, which does not match the values obtained from hardware during EA. Replace those values with CPU addresses, since in reality we have a 1:1 mapping between the two. Signed-off-by: Kornel Duleba <redacted>Claudiu, Do you have any comment on this?
Well, probing is still working with this change, I've just tested it. PCI listing at boot time changes from: pci-host-generic 1f0000000.pcie: host bridge /soc/pcie@1f0000000 ranges: pci-host-generic 1f0000000.pcie: MEM 0x01f8000000..0x01f815ffff -> 0x0000000000 pci-host-generic 1f0000000.pcie: MEM 0x01f8160000..0x01f81cffff -> 0x0000000000 to: pci-host-generic 1f0000000.pcie: host bridge /soc/pcie@1f0000000 ranges: pci-host-generic 1f0000000.pcie: MEM 0x01f8000000..0x01f815ffff -> 0x01f8000000 pci-host-generic 1f0000000.pcie: MEM 0x01f8160000..0x01f81cffff -> 0x01f8160000 and looks reasonable. Adding Vladimir and Alex just in case. Acked-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Shawnquoted
--- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 262fbad8f0ec..85c62a6fabb6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi@@ -994,19 +994,19 @@ pcie@1f0000000 { /* Integrated Endpoint Root Complex */ msi-map = <0 &its 0x17 0xe>; iommu-map = <0 &smmu 0x17 0xe>; /* PF0-6 BAR0 - non-prefetchable memory */ - ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 + ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 /* PF0-6 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 + 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 + 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 /* PF0: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 + 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 + 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 /* PF1: VF0-1 BAR2 - prefetchable memory */ - 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 + 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 /* BAR4 (PF5) - non-prefetchable memory */ - 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; + 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; enetc_port0: ethernet@0,0 { compatible = "fsl,enetc"; --2.31.1
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