On 01/04/21 01:57PM, Vignesh Raghavendra wrote:

On 3/29/21 11:52 PM, Pratyush Yadav wrote:

quoted

quoted

quoted

+  cdns,fifo-depth:
+    description:
+      Size of the data FIFO in words.
+    $ref: "/schemas/types.yaml#/definitions/uint32"
+    enum: [ 128, 256 ]
+    default: 128
+
+  cdns,fifo-width:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Bus width of the data FIFO in bytes.
+    default: 4

I assume there's some constraints on this?

IIUC this is a matter of how the peripheral is implemented and there are 
no clear constraints. Different implementations can use different bus 
widths for the SRAM bus but I don't see any mention of minimum or 
maximum values. FWIW, all users in the kernel use a 4 byte bus.

IMO a safe constraint would be to set a range of 1 to 4 (8/16/24/32 bit
wide) given this represents SRAM bus width. Binding can always be
updated if there exists an implementation with higher SRAM bus
width/fifo-width (although that's highly unlikely given there are no
such examples today).

But leaving it open ended with range of 0 to UINT_MAX sounds incorrect
to me.

Ok. Will respin.

quoted

quoted

With that,

Reviewed-by: Rob Herring <robh@kernel.org>

Thanks.

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

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