From: Kishon Vijay Abraham I <hidden> Date: 2021-03-25 09:01:41
Keystone driver is used by K2G and AM65 and the interrupt handling of
both of them is different. Add support to handle legacy interrupt for
both K2G and AM65 here.
Some discussions regarding this was already done here [1] and it was
around having pulse interrupt for legacy interrupt.
The HW interrupt line connected to GIC is a pulse interrupt whereas
the legacy interrupts by definition is level interrupt. In order to
provide level interrupt functionality to edge interrupt line, PCIe
in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.
Patch series also includes converting AM65 binding to YAML and an
errata applicable for i2037.
[1] -> https://lore.kernel.org/linux-arm-kernel/20190221101518.22604-4-kishon@ti.com/
Kishon Vijay Abraham I (6):
dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's
AM65 SoC
dt-bindings: PCI: ti,am65: Add PCIe endpoint mode dt-bindings for TI's
AM65 SoC
irqdomain: Export of_phandle_args_to_fwspec()
PCI: keystone: Convert to using hierarchy domain for legacy interrupts
PCI: keystone: Add PCI legacy interrupt support for AM654
PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
.../bindings/pci/ti,am65-pci-ep.yaml | 80 ++++
.../bindings/pci/ti,am65-pci-host.yaml | 111 ++++++
drivers/pci/controller/dwc/pci-keystone.c | 343 +++++++++++++-----
include/linux/irqdomain.h | 2 +
kernel/irq/irqdomain.c | 6 +-
5 files changed, 440 insertions(+), 102 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
--
2.17.1
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From: Rob Herring <robh@kernel.org> Date: 2021-03-25 16:57:07
On Thu, 25 Mar 2021 14:30:21 +0530, Kishon Vijay Abraham I wrote:
Add PCIe host mode dt-bindings for TI's AM65 SoC.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
.../bindings/pci/ti,am65-pci-host.yaml | 111 ++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/pci/ti,am65-pci-host.example.dts:44.35-36 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:349: Documentation/devicetree/bindings/pci/ti,am65-pci-host.example.dt.yaml] Error 1
make: *** [Makefile:1380: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1458243
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
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@@ -0,0 +1,111 @@+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/+%YAML1.2+---+$id:"http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#"+$schema:"http://devicetree.org/meta-schemas/core.yaml#"++title:TI AM65 PCI Host++maintainers:+-Kishon Vijay Abraham I <kishon@ti.com>++allOf:+-$ref:/schemas/pci/pci-bus.yaml#++properties:+compatible:+enum:+-ti,am654-pcie-rc++reg:+maxItems:4++reg-names:+items:+-const:app+-const:dbics
Please use 'dbi' like everyone else if this isn't shared with the other
TI DW PCI bindings.
I'm just converting existing binding in pci-keystone.txt to yaml.
Documentation/devicetree/bindings/pci/pci-keystone.txt
Device tree for AM65 is also already in the upstream kernel.
I can try to remove the am65 specific part from pci-keystone.txt
quoted
+ - const: config
+ - const: atu
+
+ power-domains:
+ maxItems: 1
+
+ ti,syscon-pcie-id:
+ description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ ti,syscon-pcie-mode:
+ description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ msi-map: true
+
+ dma-coherent: true
+
+patternProperties:
+ "interrupt-controller":
@@ -0,0 +1,111 @@+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/+%YAML1.2+---+$id:"http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#"+$schema:"http://devicetree.org/meta-schemas/core.yaml#"++title:TI AM65 PCI Host++maintainers:+-Kishon Vijay Abraham I <kishon@ti.com>++allOf:+-$ref:/schemas/pci/pci-bus.yaml#++properties:+compatible:+enum:+-ti,am654-pcie-rc++reg:+maxItems:4++reg-names:+items:+-const:app+-const:dbics
Please use 'dbi' like everyone else if this isn't shared with the other
TI DW PCI bindings.
I'm just converting existing binding in pci-keystone.txt to yaml.
Documentation/devicetree/bindings/pci/pci-keystone.txt
Device tree for AM65 is also already in the upstream kernel.
I can try to remove the am65 specific part from pci-keystone.txt
Can you remove pci-keystone.txt entirely. That's what 'converting' means.
Rob
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From: Kishon Vijay Abraham I <hidden> Date: 2021-03-25 09:01:41
Export of_phandle_args_to_fwspec() to be used by drivers.
of_phandle_args_to_fwspec() can be used by drivers to get irq specifier
from device node useful while creating hierarchy domain. This was
suggested by Marc Zyngier [1].
[1] -> http://lore.kernel.org/r/20190223121143.14c1f150@why.wild-wind.fr.eu.org/
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
include/linux/irqdomain.h | 2 ++
kernel/irq/irqdomain.c | 6 +++---
2 files changed, 5 insertions(+), 3 deletions(-)
From: Kishon Vijay Abraham I <hidden> Date: 2021-03-25 09:01:41
Add PCI legacy interrupt support for AM654. AM654 has a single HW
interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
The HW interrupt line connected to GIC is a pulse interrupt whereas
the legacy interrupts by definition is level interrupt. In order to
provide level interrupt functionality to edge interrupt line, PCIe
in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/controller/dwc/pci-keystone.c | 87 +++++++++++++++++++++--
1 file changed, 82 insertions(+), 5 deletions(-)
@@ -728,6 +752,54 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie)returnret;}+staticintks_pcie_am654_intx_map(structirq_domain*domain,unsignedintirq,+irq_hw_number_thwirq)+{+irq_set_chip_and_handler(irq,&dummy_irq_chip,handle_simple_irq);+irq_set_chip_data(irq,domain->host_data);++return0;+}++staticconststructirq_domain_opsks_pcie_am654_irq_domain_ops={+.map=ks_pcie_am654_intx_map,+};++staticintks_pcie_am654_config_legacy_irq(structkeystone_pcie*ks_pcie)+{+structdevice*dev=ks_pcie->pci->dev;+structirq_domain*legacy_irq_domain;+structdevice_node*np=ks_pcie->np;+structdevice_node*intc_np;+intret=0;+intirq;+inti;++intc_np=of_get_child_by_name(np,"interrupt-controller");+if(!intc_np){+dev_warn(dev,"legacy interrupt-controller node is absent\n");+return-EINVAL;+}++irq=irq_of_parse_and_map(intc_np,0);+if(!irq)+return-EINVAL;++irq_set_chained_handler_and_data(irq,ks_pcie_am654_legacy_irq_handler,ks_pcie);+legacy_irq_domain=irq_domain_add_linear(intc_np,PCI_NUM_INTX,+&ks_pcie_am654_irq_domain_ops,ks_pcie);+if(!legacy_irq_domain){+dev_err(dev,"Failed to add irq domain for legacy irqs\n");+return-EINVAL;+}+ks_pcie->legacy_irq_domain=legacy_irq_domain;++for(i=0;i<PCI_NUM_INTX;i++)+ks_pcie_app_writel(ks_pcie,IRQ_ENABLE_SET(i),INTx_EN);++returnret;+}+staticintks_pcie_config_legacy_irq(structkeystone_pcie*ks_pcie){structdevice*dev=ks_pcie->pci->dev;
@@ -835,12 +907,17 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)intret;pp->bridge->ops=&ks_pcie_ops;-if(!ks_pcie->is_am6)-pp->bridge->child_ops=&ks_child_pcie_ops;-ret=ks_pcie_config_legacy_irq(ks_pcie);-if(ret)-returnret;+if(!ks_pcie->is_am6){+pp->bridge->child_ops=&ks_child_pcie_ops;+ret=ks_pcie_config_legacy_irq(ks_pcie);+if(ret)+returnret;+}else{+ret=ks_pcie_am654_config_legacy_irq(ks_pcie);+if(ret)+returnret;+}ret=ks_pcie_config_msi_irq(ks_pcie);if(ret)
--
2.17.1
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From: Krzysztof Wilczyński <hidden> Date: 2021-03-26 07:15:06
Hi Kishon,
[...]
+ if (!legacy_irq_domain) {
+ dev_err(dev, "Failed to add irq domain for legacy irqs\n");
+ return -EINVAL;
+ }
[...]
It would be "IRQ" and "IRQs" in the message above.
[...]
- ret = ks_pcie_config_legacy_irq(ks_pcie);
- if (ret)
- return ret;
+ if (!ks_pcie->is_am6) {
+ pp->bridge->child_ops = &ks_child_pcie_ops;
+ ret = ks_pcie_config_legacy_irq(ks_pcie);
+ if (ret)
+ return ret;
+ } else {
+ ret = ks_pcie_am654_config_legacy_irq(ks_pcie);
+ if (ret)
+ return ret;
+ }
[...]
What if we change this to the following:
if (!ks_pcie->is_am6) {
pp->bridge->child_ops = &ks_child_pcie_ops;
ret = ks_pcie_config_legacy_irq(ks_pcie);
} else {
ret = ks_pcie_am654_config_legacy_irq(ks_pcie);
}
if (ret)
return ret;
Not sure if this is something you would prefer, but it seems that either
of the functions can set "ret", so checking immediately after would be
the same as checking in either of the branches. But, this is a matter
of style, so it would be up to you - not sure what do you prefer.
Krzysztof
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From: Marc Zyngier <maz@kernel.org> Date: 2021-04-02 11:11:37
On Thu, 25 Mar 2021 09:00:25 +0000,
Kishon Vijay Abraham I [off-list ref] wrote:
quoted hunk
Add PCI legacy interrupt support for AM654. AM654 has a single HW
interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
The HW interrupt line connected to GIC is a pulse interrupt whereas
the legacy interrupts by definition is level interrupt. In order to
provide level interrupt functionality to edge interrupt line, PCIe
in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/controller/dwc/pci-keystone.c | 87 +++++++++++++++++++++--
1 file changed, 82 insertions(+), 5 deletions(-)
What are these writes for? The first one feels like an Ack, and the
second one has EOI written over it.
If that's what they are, llease move these to a proper irq_chip
structure and use the appropriate flow handler, instead of
dummy_irq_chip and handle_simple_irq.
Thanks,
M.
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From: Kishon Vijay Abraham I <hidden> Date: 2021-03-25 09:01:41
Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
(SPRZ452D–July 2018–Revised December 2019 [1]) mentions when an
inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
the bus may corrupt the packet payload and the corrupt data may
cause associated applications or the processor to hang.
The workaround for Errata #i2037 is to limit the maximum read
request size and maximum payload size to 128 Bytes. Add workaround
for Errata #i2037 here. The errata and workaround is applicable
only to AM65x SR 1.0 and later versions of the silicon will have
this fixed.
[1] -> http://www.ti.com/lit/er/sprz452d/sprz452d.pdf
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/controller/dwc/pci-keystone.c | 42 +++++++++++++++++++++++
1 file changed, 42 insertions(+)
From: Krzysztof Wilczyński <hidden> Date: 2021-03-26 07:19:52
Hi Kishon,
A few small nitpicks.
Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
(SPRZ452D–July 2018–Revised December 2019 [1]) mentions when an
inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
the bus may corrupt the packet payload and the corrupt data may
cause associated applications or the processor to hang.
The workaround for Errata #i2037 is to limit the maximum read
request size and maximum payload size to 128 Bytes. Add workaround
for Errata #i2037 here. The errata and workaround is applicable
only to AM65x SR 1.0 and later versions of the silicon will have
this fixed.
I think it would be either "128 B" or "128 bytes", there is no need to
capitalise bytes.
[...]
+ /*
+ * Memory transactions fail with PCI controller in AM654 PG1.0
+ * when MRRS is set to more than 128 Bytes. Force the MRRS to
+ * 128 Bytes in all downstream devices.
+ */
Same here, it would be "128 bytes" in the comment above.
[...]
+ if (pcie_get_readrq(dev) > 128) {
+ dev_info(&dev->dev, "limiting MRRS to 128\n");
+ pcie_set_readrq(dev, 128);
+ }
From: Rob Herring <robh@kernel.org> Date: 2021-03-25 16:57:07
On Thu, 25 Mar 2021 14:30:22 +0530, Kishon Vijay Abraham I wrote:
Add PCIe endpoint mode dt-bindings for TI's AM65 SoC.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
.../bindings/pci/ti,am65-pci-ep.yaml | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/pci/ti,am65-pci-ep.example.dts:39.35-36 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:349: Documentation/devicetree/bindings/pci/ti,am65-pci-ep.example.dt.yaml] Error 1
make: *** [Makefile:1380: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1458245
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
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From: Kishon Vijay Abraham I <hidden> Date: 2021-03-25 09:02:11
K2G provides separate IRQ lines for each of the four legacy interrupts.
Model this using hierarchy domain instead of linear domain with chained
IRQ handler.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/controller/dwc/pci-keystone.c | 214 ++++++++++++----------
1 file changed, 120 insertions(+), 94 deletions(-)
@@ -253,26 +252,6 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp)returndw_pcie_allocate_domains(pp);}-staticvoidks_pcie_handle_legacy_irq(structkeystone_pcie*ks_pcie,-intoffset)-{-structdw_pcie*pci=ks_pcie->pci;-structdevice*dev=pci->dev;-u32pending;-intvirq;--pending=ks_pcie_app_readl(ks_pcie,IRQ_STATUS(offset));--if(BIT(0)&pending){-virq=irq_linear_revmap(ks_pcie->legacy_irq_domain,offset);-dev_dbg(dev,": irq: irq_offset %d, virq %d\n",offset,virq);-generic_handle_irq(virq);-}--/* EOI the INTx interrupt */-ks_pcie_app_writel(ks_pcie,IRQ_EOI,offset);-}-staticvoidks_pcie_enable_error_irq(structkeystone_pcie*ks_pcie){ks_pcie_app_writel(ks_pcie,ERR_IRQ_ENABLE_SET,ERR_IRQ_ALL);
@@ -310,39 +289,120 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)returnIRQ_HANDLED;}-staticvoidks_pcie_ack_legacy_irq(structirq_data*d)+voidks_pcie_irq_eoi(structirq_data*data){+structkeystone_pcie*ks_pcie=irq_data_get_irq_chip_data(data);+irq_hw_number_thwirq=data->hwirq;++ks_pcie_app_writel(ks_pcie,IRQ_EOI,hwirq);+irq_chip_eoi_parent(data);}-staticvoidks_pcie_mask_legacy_irq(structirq_data*d)+voidks_pcie_irq_enable(structirq_data*data){+structkeystone_pcie*ks_pcie=irq_data_get_irq_chip_data(data);+irq_hw_number_thwirq=data->hwirq;++ks_pcie_app_writel(ks_pcie,IRQ_ENABLE_SET(hwirq),INTx_EN);+irq_chip_enable_parent(data);}-staticvoidks_pcie_unmask_legacy_irq(structirq_data*d)+voidks_pcie_irq_disable(structirq_data*data){+structkeystone_pcie*ks_pcie=irq_data_get_irq_chip_data(data);+irq_hw_number_thwirq=data->hwirq;++ks_pcie_app_writel(ks_pcie,IRQ_ENABLE_CLR(hwirq),INTx_EN);+irq_chip_disable_parent(data);}staticstructirq_chipks_pcie_legacy_irq_chip={-.name="Keystone-PCI-Legacy-IRQ",-.irq_ack=ks_pcie_ack_legacy_irq,-.irq_mask=ks_pcie_mask_legacy_irq,-.irq_unmask=ks_pcie_unmask_legacy_irq,+.name="Keystone-PCI-Legacy-IRQ",+.irq_enable=ks_pcie_irq_enable,+.irq_disable=ks_pcie_irq_disable,+.irq_eoi=ks_pcie_irq_eoi,+.irq_mask=irq_chip_mask_parent,+.irq_unmask=irq_chip_unmask_parent,+.irq_retrigger=irq_chip_retrigger_hierarchy,+.irq_set_type=irq_chip_set_type_parent,+.irq_set_affinity=irq_chip_set_affinity_parent,};-staticintks_pcie_init_legacy_irq_map(structirq_domain*d,-unsignedintirq,-irq_hw_number_thw_irq)+staticintks_pcie_legacy_irq_domain_alloc(structirq_domain*domain,unsignedintvirq,+unsignedintnr_irqs,void*data){-irq_set_chip_and_handler(irq,&ks_pcie_legacy_irq_chip,-handle_level_irq);-irq_set_chip_data(irq,d->host_data);+structkeystone_pcie*ks_pcie=domain->host_data;+structdevice_node*np=ks_pcie->legacy_intc_np;+structirq_fwspecparent_fwspec,*fwspec=data;+structof_phandle_argsout_irq;+intret;++if(nr_irqs!=1)+return-EINVAL;++/*+*Getthecorrectinterruptfromlegacy-interrupt-controllernode+*correspondingtoINTA/INTB/INTC/INTD(passedinfwspec->param[0])+*afterperformingmappingspecifiedin"interrupt-map".+*interrupt-map=<0001&pcie_intc00>,INTA(4thcellin+*interrupt-map)correspondsto1stentryin"interrupts"(6thcell+*ininterrupt-map)+*/+ret=of_irq_parse_one(np,fwspec->param[0],&out_irq);+if(ret<0){+pr_err("Failed to parse interrupt node\n");+returnret;+}++of_phandle_args_to_fwspec(np,out_irq.args,out_irq.args_count,&parent_fwspec);++ret=irq_domain_alloc_irqs_parent(domain,virq,1,&parent_fwspec);+if(ret<0){+pr_err("Failed to allocate parent irq %u: %d\n",+parent_fwspec.param[0],ret);+returnret;+}++ret=irq_domain_set_hwirq_and_chip(domain,virq,fwspec->param[0],+&ks_pcie_legacy_irq_chip,ks_pcie);+if(ret<0){+pr_err("Failed to set hwirq and chip\n");+gotoerr_set_hwirq_and_chip;+}return0;++err_set_hwirq_and_chip:+irq_domain_free_irqs_parent(domain,virq,1);++returnret;+}++staticintks_pcie_irq_domain_translate(structirq_domain*domain,+structirq_fwspec*fwspec,+unsignedlong*hwirq,+unsignedint*type)+{+if(is_of_node(fwspec->fwnode)){+if(fwspec->param_count!=2)+return-EINVAL;++if(fwspec->param[0]>=PCI_NUM_INTX)+return-EINVAL;++*hwirq=fwspec->param[0];+*type=fwspec->param[1];++return0;+}++return-EINVAL;}staticconststructirq_domain_opsks_pcie_legacy_irq_domain_ops={-.map=ks_pcie_init_legacy_irq_map,-.xlate=irq_domain_xlate_onetwocell,+.alloc=ks_pcie_legacy_irq_domain_alloc,+.free=irq_domain_free_irqs_common,+.translate=ks_pcie_irq_domain_translate,};/**
@@ -702,20 +733,33 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie)structdevice*dev=ks_pcie->pci->dev;structirq_domain*legacy_irq_domain;structdevice_node*np=ks_pcie->np;+structirq_domain*parent_domain;+structdevice_node*parent_node;structdevice_node*intc_np;-intirq_count,irq,ret=0,i;+intirq_count,ret=0;-intc_np=of_get_child_by_name(np,"legacy-interrupt-controller");+intc_np=of_get_child_by_name(np,"interrupt-controller");if(!intc_np){-/*-*Sincelegacyinterruptsaremodeledasedge-interruptsin-*AM6,keepitdisabledfornow.-*/-if(ks_pcie->is_am6)-return0;dev_warn(dev,"legacy-interrupt-controller node is absent\n");return-EINVAL;}+ks_pcie->legacy_intc_np=intc_np;++parent_node=of_irq_find_parent(intc_np);+if(!parent_node){+dev_err(dev,"unable to obtain parent node\n");+ret=-ENXIO;+gotoerr;+}++parent_domain=irq_find_host(parent_node);+if(!parent_domain){+dev_err(dev,"unable to obtain parent domain\n");+ret=-ENXIO;+gotoerr;+}++of_node_put(parent_node);irq_count=of_irq_count(intc_np);if(!irq_count){
@@ -724,31 +768,13 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie)gotoerr;}-for(i=0;i<irq_count;i++){-irq=irq_of_parse_and_map(intc_np,i);-if(!irq){-ret=-EINVAL;-gotoerr;-}-ks_pcie->legacy_host_irqs[i]=irq;--irq_set_chained_handler_and_data(irq,-ks_pcie_legacy_irq_handler,-ks_pcie);-}--legacy_irq_domain=-irq_domain_add_linear(intc_np,PCI_NUM_INTX,-&ks_pcie_legacy_irq_domain_ops,NULL);+legacy_irq_domain=irq_domain_add_hierarchy(parent_domain,0,PCI_NUM_INTX,intc_np,+&ks_pcie_legacy_irq_domain_ops,ks_pcie);if(!legacy_irq_domain){dev_err(dev,"Failed to add irq domain for legacy irqs\n");ret=-EINVAL;gotoerr;}-ks_pcie->legacy_irq_domain=legacy_irq_domain;--for(i=0;i<PCI_NUM_INTX;i++)-ks_pcie_app_writel(ks_pcie,IRQ_ENABLE_SET(i),INTx_EN);err:of_node_put(intc_np);
--
2.17.1
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From: Krzysztof Wilczyński <hidden> Date: 2021-03-26 06:58:58
Hi Kishon,
Thank you for sending the series over!
A few small nitpick, so feel free to ignore it.
[...]
+ ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
+ if (ret < 0) {
+ pr_err("Failed to allocate parent irq %u: %d\n",
+ parent_fwspec.param[0], ret);
+ return ret;
[...]
Use "IRQ" in the message above.
Also, the error messages with both starting with upper- and lower- case
letter, not sure if this is because of dev_err() vs pr_err(), but if
there is no significance between these two methods, then it might be
nice to keep the style consistent.
Krzysztof
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From: Christian Gmeiner <christian.gmeiner@gmail.com> Date: 2021-05-17 13:15:46
Hi
Am Do., 25. März 2021 um 10:04 Uhr schrieb Kishon Vijay Abraham I
[off-list ref]:
Keystone driver is used by K2G and AM65 and the interrupt handling of
both of them is different. Add support to handle legacy interrupt for
both K2G and AM65 here.
Some discussions regarding this was already done here [1] and it was
around having pulse interrupt for legacy interrupt.
The HW interrupt line connected to GIC is a pulse interrupt whereas
the legacy interrupts by definition is level interrupt. In order to
provide level interrupt functionality to edge interrupt line, PCIe
in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.
Patch series also includes converting AM65 binding to YAML and an
errata applicable for i2037.
[1] -> https://lore.kernel.org/linux-arm-kernel/20190221101518.22604-4-kishon@ti.com/
Kishon Vijay Abraham I (6):
dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's
AM65 SoC
dt-bindings: PCI: ti,am65: Add PCIe endpoint mode dt-bindings for TI's
AM65 SoC
irqdomain: Export of_phandle_args_to_fwspec()
PCI: keystone: Convert to using hierarchy domain for legacy interrupts
PCI: keystone: Add PCI legacy interrupt support for AM654
PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
.../bindings/pci/ti,am65-pci-ep.yaml | 80 ++++
.../bindings/pci/ti,am65-pci-host.yaml | 111 ++++++
drivers/pci/controller/dwc/pci-keystone.c | 343 +++++++++++++-----
include/linux/irqdomain.h | 2 +
kernel/irq/irqdomain.c | 6 +-
5 files changed, 440 insertions(+), 102 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
--
2.17.1
From: Kishon Vijay Abraham I <hidden> Date: 2021-05-17 13:21:26
Hi Christian,
On 17/05/21 6:45 pm, Christian Gmeiner wrote:
Hi
Am Do., 25. März 2021 um 10:04 Uhr schrieb Kishon Vijay Abraham I
[off-list ref]:
quoted
Keystone driver is used by K2G and AM65 and the interrupt handling of
both of them is different. Add support to handle legacy interrupt for
both K2G and AM65 here.
Some discussions regarding this was already done here [1] and it was
around having pulse interrupt for legacy interrupt.
The HW interrupt line connected to GIC is a pulse interrupt whereas
the legacy interrupts by definition is level interrupt. In order to
provide level interrupt functionality to edge interrupt line, PCIe
in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
register after handling the interrupt, the IP checks the state of
legacy interrupt and re-triggers pulse interrupt invoking the handler
again.
Patch series also includes converting AM65 binding to YAML and an
errata applicable for i2037.
[1] -> https://lore.kernel.org/linux-arm-kernel/20190221101518.22604-4-kishon@ti.com/
Kishon Vijay Abraham I (6):
dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's
AM65 SoC
dt-bindings: PCI: ti,am65: Add PCIe endpoint mode dt-bindings for TI's
AM65 SoC
irqdomain: Export of_phandle_args_to_fwspec()
PCI: keystone: Convert to using hierarchy domain for legacy interrupts
PCI: keystone: Add PCI legacy interrupt support for AM654
PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
.../bindings/pci/ti,am65-pci-ep.yaml | 80 ++++
.../bindings/pci/ti,am65-pci-host.yaml | 111 ++++++
drivers/pci/controller/dwc/pci-keystone.c | 343 +++++++++++++-----
include/linux/irqdomain.h | 2 +
kernel/irq/irqdomain.c | 6 +-
5 files changed, 440 insertions(+), 102 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
--
2.17.1
Is there somewhere an updated version of this patch series?
I haven't posted an updated version yet. My plan was to re-work and post
it by early June.
Thanks
Kishon
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