On 12/03/21 02:32PM, Michael Walle wrote:

Am 2021-03-11 20:12, schrieb Pratyush Yadav:

quoted

The main problem here is telling the controller where to find the
pattern and how to read it. This RFC uses nvmem cells which point to a
fixed partition containing the data to do the reads. It depends on [0]
and [1].

The obvious problem with this is it won't work when the partitions are
defined via command line. I don't see any good way to add nvmem cells to
command line partitions. I would like some help or ideas here. We don't
necessarily have to use nvmem either. Any way that can cleanly and
consistently let the controller find out where the pattern is stored is
good.

The NXP LS1028A SoC has a similar calibration (although there its done
in hardware it seems) and there the datasheet mentions there are flash
devices which supports a preamble before a read function. The preamble
is then some kind of learning pattern. Did you see a flash which actually
supports that in the wild? I can't find any publicly available datasheets
of 8bit I/O SPI NOR flashes.

I haven't seen any such flash but it looks like Tudor has.

-michael

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

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