Hi,
Now that the OSPI controller driver and the SPI NOR core have support
for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR
transactions.
Pratyush Yadav (3):
arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 4 +--
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 +--
4 files changed, 57 insertions(+), 4 deletions(-)
--
2.30.0
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Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the
frequency to 25 MHz. This is the frequency that the flash has been
successfully tested with in Octal DTR mode. The total performance should
still increase since 8D-8D-8D mode should be at least twice as fast as
1S-1S-8S mode.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
No changes in v2.
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the
frequency to 25 MHz. This is the frequency that the flash has been
successfully tested with in Octal DTR mode. The total performance should
still increase since 8D-8D-8D mode should be at least twice as fast as
1S-1S-8S mode.
Signed-off-by: Pratyush Yadav <redacted>
---
Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the
frequency to 25 MHz. This is the frequency that the flash has been
successfully tested with in Octal DTR mode. The total performance should
still increase since 8D-8D-8D mode should be at least twice as fast as
1S-1S-8S mode.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
No changes in v2.
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the
frequency to 25 MHz. This is the frequency that the flash has been
successfully tested with in Octal DTR mode. The total performance should
still increase since 8D-8D-8D mode should be at least twice as fast as
1S-1S-8S mode.
Signed-off-by: Pratyush Yadav <redacted>
---
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
Changes in v2:
- Do not force a pulldown on the DQS line because it already has a
pulldown resistor.
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
2 files changed, 53 insertions(+)
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
Changes in v2:
- Do not force a pulldown on the DQS line because it already has a
pulldown resistor.
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
2 files changed, 53 insertions(+)
TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
Changes in v2:
- Do not force a pulldown on the DQS line because it already has a
pulldown resistor.
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
2 files changed, 53 insertions(+)
I see this:
+/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+'
And that is because
Documentation/devicetree/bindings/spi/cadence-quadspi.txt is not
converted to yaml. Following the new stringent rules, yaml please?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
Changes in v2:
- Do not force a pulldown on the DQS line because it already has a
pulldown resistor.
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
2 files changed, 53 insertions(+)
I see this:
+/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+'
And that is because
Documentation/devicetree/bindings/spi/cadence-quadspi.txt is not
converted to yaml. Following the new stringent rules, yaml please?
Ok. I am working on the conversion. Will send it soon.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
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TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
Changes in v2:
- Do not force a pulldown on the DQS line because it already has a
pulldown resistor.
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
2 files changed, 53 insertions(+)
I see this:
+/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+'
And that is because
Documentation/devicetree/bindings/spi/cadence-quadspi.txt is not
converted to yaml. Following the new stringent rules, yaml please?
Ok. I am working on the conversion. Will send it soon.
OK I am keeping to our old rule that as long as binding is pre-existing
and they are in Documentation/devicetree/ we are picking the node up..
new bindings absolutely must be in yaml.
But really, it is high time these txt files get converted to yaml..
Lets use this current collection for 5.13-rc1 cycle as the last window
where we permit this.
* 5.14-rc1 cycle patches, lets make sure: no txt file bindings, yaml at
least in next
* 5.15-rc1 cycle patches, yaml binding must be in master OR a immutable
tag from subsystem maintainer.
new bindings already need to be yaml.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.
Signed-off-by: Pratyush Yadav <redacted>
---
Notes:
Changes in v2:
- Do not force a pulldown on the DQS line because it already has a
pulldown resistor.
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
2 files changed, 53 insertions(+)
I see this with dtbs_check on v5.12-rc2:
/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+'
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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On Fri, 5 Mar 2021 21:09:23 +0530, Pratyush Yadav wrote:
Now that the OSPI controller driver and the SPI NOR core have support
for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR
transactions.
Pratyush Yadav (3):
arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
[...]
Hi Pratyush Yadav,
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
commit: 4c20ee99dd1a36ab89c6a8c51ed25e9328d8a8cc
[2/3] arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
commit: 7c172b30a540644fa53051e947d6712be5d6d6ce
[3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
commit: efbdf2e9183bd5e75c64d251c6b673ca61ea01b3
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
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