On Fri, Jan 29, 2021 at 11:53:20AM +0100, Arnd Bergmann wrote:

On Fri, Jan 29, 2021 at 11:33 AM Russell King - ARM Linux admin
[off-list ref] wrote:

quoted

It is safer to put explicit barriers where it is necessary.

Also remember that the barrier in readl() etc is _after_ the read, not
before, and the barrier in writel() is _before_ the write, not after.
The point is to ensure that DMA memory accesses are properly ordered
with the IO-accessing instructions.

So, using readl_relaxed() with a read-modify-write is entirely sensible
provided you do not access DMA memory inbetween.

The part I was not sure about is what happens when you have
a store to memory immediately before flushing the cache, and there
are no barriers inbetween.

If the caches are non-coherent, we have to flush L1 before we flush L2
to ensure writebacks get pushed out properly, and L1 will already have
the necessary barriers.

If we have the situation where L1 is coherent but L2 isn't, then I think
we have an "interesting situation" that we haven't considered whether it
be in DT or elsewhere.

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