Thread (24 messages) 24 messages, 3 authors, 2021-02-03

Re: [PATCH 4/8] drivers/perf: hisi: Add new functions for HHA PMU

From: Shaokun Zhang <hidden>
Date: 2021-01-27 08:04:28

Hi John,

在 2021/1/26 20:10, John Garry 写道:
On 31/12/2020 06:19, Shaokun Zhang wrote:
quoted
On HiSilicon Hip09 platform, some new functions are also supported on
HHA PMU, it can filter gathered statistics by the Master ID and mask
from the SoC if the user wants to do deep-going profiling.
Tracetag support is also added with L3C PMU in the SoC system.

$# perf stat -a -e hisi_sccl3_hha0/config=0x02,tracetag_en=0x1/ sleep 5

$# perf stat -a -e hisi_sccl3_hha0/config=0x02,srcid_cmd=0x1/ sleep 5
Much more introduction is added in documentation:

quoted
Documentation/admin-guide/perf/hisi-pmu.rst
I think that it would make sense to add that prior to the driver change, like how we do with dt
bindings, but not so important
I will consider this.
quoted
Cc: Mark Rutland<mark.rutland@arm.com>
Cc: Will Deacon<will@kernel.org>
Cc: John Garry<redacted>
Cc: Jonathan Cameron<Jonathan.Cameron@huawei.com>
Co-developed-by: Qi Liu<redacted>
Signed-off-by: Qi Liu<redacted>
Signed-off-by: Shaokun Zhang<redacted>
Reviewed-by: John Garry <redacted>

I suppose the change in hisi_hha_pmu_init_data() is ok (not shown).
quoted
---
  drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 203 +++++++++++++++++++++++++--
  1 file changed, 188 insertions(+), 15 deletions(-)
diff --git a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
index 2f55e5864d39..5e1c4b61ffce 100644
--- a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
@@ -25,19 +25,136 @@
  #define HHA_VERSION        0x1cf0
  #define HHA_PERF_CTRL        0x1E00
  #define HHA_EVENT_CTRL        0x1E04
+#define HHA_SRCID_CTRL        0x1E08
+#define HHA_DATSRC_CTRL        0x1BF0
  #define HHA_EVENT_TYPE0        0x1E80
  /*
- * Each counter is 48-bits and [48:63] are reserved
- * which are Read-As-Zero and Writes-Ignored.
+ * If the HW version only supports a 48-bit counter, then
+ * bits [63:48] are reserved, which are Read-As-Zero and
+ * Writes-Ignored.
   */
  #define HHA_CNT0_LOWER        0x1F00
  -/* HHA has 16-counters */
+/* HHA PMU v1 has 16-counter and v2 only has 8-counter */
nit: "has 16 counters and v2 has only 8 counters */
Ok,

Thanks,
Shaokun
.
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