[RFC PATCH v1 2/5] arm64: cpufeature: Add an API to get level of TTRem supported by hardware
From: Yanan Wang <hidden>
Date: 2021-01-26 13:44:02
Also in:
kvm, kvmarm, lkml
Subsystem:
arm64 port (aarch64 architecture), the rest · Maintainers:
Catalin Marinas, Will Deacon, Linus Torvalds
The ARMv8.4 architecture offers 3 levels of support when changing block size without changing any other parameters that are listed as requiring use of break-before-make. So get the current level of TTRem supported by hardware and software can use corresponding process when changing block size. Signed-off-by: Yanan Wang <redacted> --- arch/arm64/include/asm/cpufeature.h | 13 +++++++++++++ 1 file changed, 13 insertions(+)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 9a555809b89c..f8ee7d30829b 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h@@ -50,6 +50,11 @@ enum ftr_type { #define FTR_VISIBLE true /* Feature visible to the user space */ #define FTR_HIDDEN false /* Feature is hidden from the user */ +/* Supported levels of ARMv8.4 TTRem feature */ +#define TTREM_LEVEL0 0 +#define TTREM_LEVEL1 1 +#define TTREM_LEVEL2 2 + #define FTR_VISIBLE_IF_IS_ENABLED(config) \ (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
@@ -739,6 +744,14 @@ static inline bool system_supports_tlb_range(void) cpus_have_const_cap(ARM64_HAS_TLB_RANGE); } +static inline u32 system_support_level_of_ttrem(void) +{ + u64 mmfr2 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + + return cpuid_feature_extract_unsigned_field(mmfr2, + ID_AA64MMFR2_BBM_SHIFT); +} + extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
--
2.19.1
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