Re: [PATCH] arm64: dts: imx8mq: Add clock parents for mipi dphy
From: Shawn Guo <shawnguo@kernel.org>
Date: 2021-01-10 12:47:33
Also in:
linux-devicetree, lkml
On Fri, Dec 18, 2020 at 06:50:05PM +0100, Guido Günther wrote:
quoted hunk ↗ jump to hunk
This makes sure the clock tree setup for the dphy is not dependent on other components. Without this change bringing up the display can fail like kernel: phy phy-30a00300.dphy.2: Invalid CM/CN/CO values: 165/217/1 kernel: phy phy-30a00300.dphy.2: for hs_clk/ref_clk=451656000/593999998 ~ 165/217 if LCDIF doesn't set up that part of the clock tree first. This was noticed when testing the Librem 5 devkit with defconfig. It doesn't happen when modules are built in. Signed-off-by: Guido Günther <agx@sigxcpu.org> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index a841a023e8e0..ca0847e8f13c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi@@ -1016,9 +1016,14 @@ dphy: dphy@30a00300 { reg = <0x30a00300 0x100>; clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, + <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>;
You do not seem to set parent or rate on IMX8MQ_VIDEO_PLL1. Why do you have it here? Shawn
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_VIDEO_PLL1_OUT>; + assigned-clock-rates = <0>, <0>, <24000000>; #phy-cells = <0>; power-domains = <&pgc_mipi>; status = "disabled"; -- 2.29.2
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