[dropped linux-sunxi@googlegroups.com, which seems to be a closed ML]

On Sun, 03 Jan 2021 10:30:51 +0000,
Samuel Holland [off-list ref] wrote:

Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt
controllers: GIC and R_INTC. GIC does not support wakeup. R_INTC handles
the external NMI pin, and provides 32+ IRQs to the ARISC. The first 16
of these correspond 1:1 to a block of GIC IRQs starting with the NMI.
The last 13-16 multiplex the first (up to) 128 GIC SPIs.

This series replaces the existing chained irqchip driver that could only
control the NMI, with a stacked irqchip driver that also provides wakeup
capability for those multiplexed SPI IRQs. The idea is to preconfigure
the ARISC's IRQ controller, and then the ARISC firmware knows to wake up
as soon as it receives an IRQ. It can also decide how deep it can
suspend based on the selected wakeup IRQs.

Out of curiosity, how do you plan to communicate dynamic configuration
of IRQs to the ARISC? We recently went through this with some TI
stuff, and the result a bit awkward (the arm64 side configures
interrupts that are not visible to the kernel, but only to the
co-processors).

I wondered whether you had other ideas...

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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