On Tue, 8 Dec 2020 at 02:26, Andrew Jeffery [off-list ref] wrote:

Hello,

This series implements support for the MMC core clk-phase-* devicetree bindings
in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600
and is present for both the SD/MMC controller and the dedicated eMMC
controller.

v5 fixes some build issues identified by the kernel test robot.

v4 can be found here:

https://lore.kernel.org/linux-mmc/20201207142556.2045481-1-andrew@aj.id.au/ (local)

The series has had light testing on an AST2600-based platform which requires
180deg of input and output clock phase correction at HS200, as well as some
synthetic testing under qemu and KUnit.

Please review!

FYI, other than the comment I had on patch1, I think the series looks
good to me.

[...]

Kind regards
Uffe

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