[PATCH v6 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
From: Claudiu Beznea <hidden>
Date: 2020-11-19 15:44:28
Also in:
linux-clk, linux-devicetree, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: Eugen Hristev <redacted> Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Suggested-by: Claudiu Beznea <redacted> Signed-off-by: Eugen Hristev <redacted> [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] Signed-off-by: Claudiu Beznea <redacted> --- drivers/clk/at91/sama7g5.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 7ef7963126b6..d3c3469d47d9 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c@@ -117,7 +117,8 @@ static const struct { .p = "cpupll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, }, + .c = 1, + .eid = PMC_CPUPLL, }, }, [PLL_ID_SYS] = {
@@ -131,7 +132,8 @@ static const struct { .p = "syspll_fracck", .l = &pll_layout_divpmc, .t = PLL_TYPE_DIV, - .c = 1, }, + .c = 1, + .eid = PMC_SYSPLL, }, }, [PLL_ID_DDR] = {
--
2.7.4
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