Re: [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: 2020-10-14 14:04:46
Also in:
linux-devicetree, linux-edac
On Wed, Oct 14, 2020 at 08:25:11AM -0500, Rob Herring wrote:
On Tue, Oct 13, 2020 at 02:50:30PM +0200, Sascha Hauer wrote:quoted
This driver is based on an earlier version from York Sun which can be found here: https://lkml.org/lkml/2018/3/14/1203. At that time the conclusion was that this driver is not suitable for mainline as it used IMPLEMENTATION DEFINED CPU registers and also NXP specific SMC calls. All this was used for the error injection only, for error reporting it is not needed.Have you looked at Amazon's version: http://lore.kernel.org/r/20200510151310.17372-2-hhhawa@amazon.com (local)
No, I was not aware of that driver. It's basically the same driver, but limited to a single SoC. Looks like at least some things are better in that driver, read_sysreg_s(ARM_CA57_L2MERRSR_EL1) reads better than my open coded variant.
Which is an A57 EDAC driver. Looks like it never got upstream though, but it's not clear why. You'll note that it doesn't have a virtual DT node either.
Testing the SoC type in an initcall looks odd to me. Wouldn't a dedicated node be preferred? Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel