Re: [PATCH] PCI: imx6: Select correct clock source for MX7D PCIe PHY

On 9/28/20 3:39 AM, Richard Zhu wrote:
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The internal PCIe PHY clock source cannot lock the PLL, use the
external pad one just like iMX8MQ does, which is very similar SoC in this area.

[Richard Zhu] Hi Marek:
Do you know why PCIe PHY clock can't be locked when internal PLL is used as

PCIe REF CLK?

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As I know that the PCIe PHY clock can be locked on iMX7D SDB board when

internal PLL is selected.

I don't know, and I can't find any useful information which could explain it either,
nor why iMX8 does it differently (like this patch).
Maybe it is related to errata e10728 ?

[Richard Zhu] 
iMX8MQ has two PCIe controllers, and only has one pair CLK N/P pads to output the internal PLL to
EP. Thus, the external OSC is used as REF clock source for both RC and EP.
Maybe one property can be introduced to distinguish the internal PLL clock or the external OSC is used
as PCIe REF clock source. 

I am open to suggestions. I would also like to know why I need this
patch on every iMX7D board I came across so far.

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