[PATCH v5 1/6] dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
From: Roger Quadros <hidden>
Date: 2020-09-30 12:20:48
Also in:
linux-devicetree, lkml
Subsystem:
multiplexer subsystem, open firmware and flattened device tree bindings, the rest · Maintainers:
Peter Rosin, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Cc: Peter Rosin <redacted> Signed-off-by: Roger Quadros <redacted> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Peter Rosin <redacted> --- include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 146d0685a925..9047ec6bd3cf 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h@@ -68,4 +68,26 @@ #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 +/* J7200 */ + +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J7200_SERDES0_LANE3_USB 0x2 +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */
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